TCM4400 Datasheet, PDF (69/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BIT5
ULON
Table 4–40. 6-Bit TR Register
BIT4
BIT3
BIT2 BIT1 BIT0
ULCAL ULSEND DLON DLCAL DLREC
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{TR Bit Signification}
ULON:
If set to 1, this bit turns on the uplink path of the baseband codec; if cleared to 0, the
uplink path is in power-down mode.
ULCAL: When this bit is set to 1, the uplink offset autocalibration is active.
ULSEND: A transition from 0 to 1 of ULSEND initiates the emission of a burst. The burst
information data, burst length, and power level need to be loaded in the
corresponding registers using the serial interface.
DLON:
If set at 1, this bit turns on the downlink path of the baseband codec; if cleared to 0, the
downlink path is in power-down mode.
DLCAL: When this bit is set at 1, the downlink offset autocalibration is active.
DLREC:
A transition from 0 to 1 of DLREC initiates the transmission of data from the
baseband codec to the DSP using the serial interface.
BDLON
BCAL BULON
BENA
CKDL
CKUL
DLON DLCAL DLREC ULON ULCAL ULSEND
Figure 4–12. Timing Interface
4–33