TCM4400 Datasheet, PDF (38/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

Full-differential buffered signals are available at ULIP, ULIN, ULQP, and ULQN. These signals are suitable
for use in the RF circuit for generating a phase-modulated signal of the form:
s(t) = A Cos (2 Pi fc t + Phi (t, alpha))
(1)
where:
fc = the RF carrier frequency,
Phi (t, alpha) = the phase component generated by the GMSK modulator from the differential
encoded data
Timing for power up, offset calibration, data transmission, and power ramp up are driven by control bits
applied to BULON (base uplink on), BCAL (calibration), and BENA (enable) (see Figure 4–1). The entire
content of a burst, including guard bits, tail bits, and data bits, is sent by the DSP using the DSP interface
and then stored by the TCM4400 in a burst buffer. Transmission start is indicated by the control bit BENA
when BULON is active. The transmission, sequencing, and power ramp up are then controlled by an on-chip
burst timing control circuit having a one-quarter-bit timing accuracy (see Figure 4–2). All data related to a
burst to be transmitted (such as bit data, ramp-up, and ramp-down delay programmation) have to be loaded
before the rising edge of BENA.
The burst length is determined by the time during which the BENA signal is active. Effective burst length
is equal to the duration of BENA plus 32 one-quarter bits. The tail of the burst is controlled internally, which
means that the modulation is maintained for 32 one-quarter bits after BENA turns off to generate the
ramp-down sequence and complete modulation.
For each burst, the power control level can be controlled by writing the power level value, using the serial
interfaces, into the power register of the auxiliary RF power control circuitry. The power ramp-up and
ramp-down sequences are controlled by the burst sequencer while the shape of the power control is
generated internally by dedicated circuitry, which drives the power control 5-bit and 8-bit D/A converters.
To minimize phase error, the I and Q channel dc-offset can be minimized using offset calibration. Each
channel includes an offset register in which a value corresponding to the required dc offset is stored,
controlling the dc offset of the I channel and Q channel D/A converters. This value is set by a calibration
sequence. Starting and stopping the calibration sequence is controlled by the control bit BCAL using the
timing interface when BULON is active. During the calibration sequence, the digital value of I and Q is forced
to zero so that only the offset register value drives the D/A converters and a low-offset comparator senses
the dc level at the BULIP/BULIN and BULQP/BULQN outputs and modifies the content of the offset registers
to minimize the dc offset (see Figure 4–2).
Gain imbalance can be introduced between I and Q channels to allow compensation of imperfections in RF
circuits. This gain imbalance is controlled through the mean of three programmation bits (IQSEL, G1, and
G0 of baseband uplink register BULCTL).
The power-down function is controlled with two bits. The first bit (BBULW of the PWDNRG1 register),
determines whether the baseband uplink path can be powered down with external GSM transmit window
activation (BULON). The second bit (BBULPD of the PWDNREG1 register) controls the activation of the
baseband uplink path. For more information about power-down control, see Section 4.8 in this document.
4–2