TCM4400 Datasheet, PDF (49/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

4.8.2 Radio Window Activation Control
With this method, the following internal blocks are powered up with the control of two bits. The first bit
enables the window control of the block activity; the second bit enables the power down.
First bit: If cleared to 0, the function is powered down with the control of the corresponding GSM
window (BDLON/BULON terminal) and with the control of the second bit. If this first bit is
set to 1, the power down is controlled only by the second bit.
Second bit: This bit is functionally associated with the first one. When this bit is 0, the function is in
power down mode.
During transmit, the following windows are designated by the activity of the BULON terminal:
• Automatic power control (APC): bits APCW and APCPD of register AUXCTL 2 are paired.
• Baseband uplink path: bits BBULW and BBULPD of register PWDNRG1 are paired.
• External reference voltage buffers VMID: bits VMIDW and VMIDPD are paired.
During receive, the following windows are designated by the activity of the BDLON terminal:
• Automatic gain control (AGC): bits AGCW and AGCPD of register AUXCTL 2 are paired.
• Baseband downlink path: bits BBDLW and BBDLPD of register PWDNRG1 are paired.
4.8.3 External Terminal PWRDN Control
With this method, the internal blocks are powered under the control of two bits. The first bit enables the
external terminal PWRDN control of the block activity. The second bit enables the power down. Terminal
PWRDN is active high.
First bit: If cleared to 0, the function is powered down under the control of the PWRDN terminal and
under the control of the second bit. If this first bit is set to 1, the power down is controlled only
by the second bit.
Second bit: This bit is functionally associated with the first one. When this bit is loaded with 0, the
function is in power down mode.
• For the digital serial interface to the DSP, bits BBSIPN and BBSIPD of register PWDNRG2
are paired.
• For the timing interface, bits TIMGPN and TIMGPD of register PWDNRG2 are paired.
• For the auxiliary A/D converters, bits ADCPN and ADCPD of register AUXCTL1 are paired.
• For the automatic frequency control (AFC) block, bits AFCPN and AFCPD of register
AUXCTL1 are paired.
• For the external reference voltage buffers MICBIAS, bits VREFPN and VREFPD of register
PWDNRG2 are paired.
• For the internal reference band gap buffers, bit VGAPPN determines whether the band gap
power down is under control of the PWRDN bit.
4.9 DSP Voice Band Serial Interface
Voice band serial digital interface consists of a bidirectional serial port. Both receive and transmit operations
are double buffered, which allows a continuous communication stream. The serial port is fully static and,
thus, functions with any arbitrary low clocking frequency.
The transfer mode available on this port is:
Clock frequency
520 kHz
16-bit data packet
frame synchronization
4–13