TCM4400 Datasheet, PDF (46/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

The PGA output is fed to two output stages: the earphone amplifier that provides a full differential signal on
the terminals EARP/EARN, and an auxiliary amplifier that provides a single-ended signal on terminal AUXO.
Both earphone and auxiliary amplifiers can be active at the same time. The downlink voice path can be
powered down with bit VDLON of the VBCTL 2 internal register.
A sidetone path is connected between the output of the voice uplink PGA and the input of the voice downlink
PGA. This path provides seven programmable gains (1 dB, – 2dB, – 5 dB, – 8 dB, – 11 dB, – 14 dB, – 17 dB,
– 20 dB, – 23 dB) and one mute position. Sidetone path gain can be selected by programming bit at register
address 23.
AUXO
Auxiliary
Amplifier
– 6 dB
Sidetone
– 23 to 1dB
From Voice Uplink PGA
From Voice
Serial Interface
EARP
EARN
Earphone
Amplifier
0 dB
Smoothing
Filter
Volume Count
and PGA
0 + 24 dB and
– 6 + 6 dB
1-Bit DAC
Low-Pass Filter
3 dB
Sigma-Delta
Modulator
– 3 dB
SINC
Interpolation
Filter
IIR
Band Pass
Filter
fs1 = 1 MHz
fs2 = 40 KHz
fs3 = 8 KHz
Figure 4–10. Downlink Path Block Diagram
4.5 DAI Interface
This digital audio interface (DAI) consists of four terminals: SSRST, SSCLK, SSDR, and SSDX. It is
compatible with the digital audio interface described in the GSM Recommendation 11.10. This interface
offers minimum CPU overhead during audio tests and speech transcoding tests, and minimizes the extra
hardware and the number of external terminals of the mobile system (MS). With this interface, the DSP does
not have to deal with rate adaptation. In normal operation, the DSP works with an 8-kHz sampling rate with
a 16-bit word format and frame synchronization, but the DAI interface works with an 8-kHz sampling rate
with a 13-bit word format without frame synchronization. The DSP (or the MCU) does not have real time
constraints with SSRST because the reset of the internal transmitters is automatic.
The DAI is controlled with four internal bits of VBCTL3 register:
DAION: When 0, the DAI block is put in low power. When 1, the DAI block is active.
VDAI:
This bit controls the start of the clock SSCLK. The falling edges of SSRST automatically
reset the VDAI.
DAIMD 0/1: These two bits are used to switch the internal data path of the three types of DAI tests:
Tests of acoustic performance of the uplink/downlink voice path
Tests of speech decoder/DTX functions (downlink path)
Tests of speech encoder/DTX functions (uplink path)
In order to correctly execute these tests, the bits DAION/VULON/VDLON must be reset before starting the
DAI test. In the case of acoustic tests, the following must be set in sequence: DAION, VDAI, VULON, and
VDLON. In case of vocoder tests, when the speech samples are ready to be exchanged with the system
simulator, the bits DAION and VDAI must be set at the same time.
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