TCM4400 Datasheet, PDF (67/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

DLCAL: This bit is set to 1 during offset calibration of the downlink path.
DLON: When set to 1, it indicates that the downlink path is powered on.
ULX:
This bit is set to 1 during transmission of the burst in the uplink path.
ULCAL: This bit is set to 1 during offset calibration of the uplink path.
ULON: When set to 1, it indicates that the uplink path is powered on.
BUFPTR: When set to 1, it indicates that the pointer of the burst buffer is at address zero.
RAMPTR: When set to 1, it indicates that the pointer of the APC RAM is at address zero.
ADCEOC: (ADC-end of conversion) When this bit is set to 1, an ADC conversion is in process.
4.11.5 Voice Band Control Register 4 (Address 23)
Voice band control register 4 (VBCTL4) is a read/write register (see Table 4–35) and contains the four
programming bits of VDLST, as defined in Table 4–36.
Table 4–35. Voice Band Control Register 4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{VBCTL4: VOICE BAND CONTROL REGISTER 4}
ADDRESS: R/W
23
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RE RE RE RE RE RE VDLST VDLST VDLST VDLST 1 0 1 1 1 1/0
SRVD SRVD SRVD SRVD SRVD SRVD 3
2
1
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{R = 0 R = 0 R = 0 R = 0 R = 0 R = 0 R/W R/W R/W R/W}
←ACCESS TYPE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
0
0
0
0
0
0
0
0
←VALUE AT RESET
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VDLST3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ⁰
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
Table 4–36. VDLST Status
VDLST2 VDLST1 VDLST0 SIDE TONE GAIN
0
0
0
Mute
1
0
1
– 23 dB
1
0
0
– 20 dB
1
1
0
–17 dB
0
1
0
–14 dB
1
1
1
–11 dB
0
1
1
– 8 dB
0
0
0
– 5 dB (nominal)
1
0
0
– 2 dB
0
0
1
+1 dB
1
0
1
+1 dB
4–31