TCM4400 Datasheet, PDF (53/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

16
DRR
16
Data Bus
Load
Control
Logic
Load
Control
Logic
RSR
16
DXR
16
XSR
Byte/Word
Counter
Clear
Clock
Clear
Clock
Byte/Word
Counter
BDR
BFSR BCLKR BCLKX BFSX
BDX
Figure 4–11. DSP Serial Digital Interface
4.10.5 DSP/MCU Serial Interface Operation and Format
The DSP/MCU serial interface configures the GSM baseband and voice ADCs and DACs (read and write
operation in internal registers), and transmits RF data to the DSP during reception of a burst by the downlink
path of the GSM baseband and voice A/D and D/A circuitry.
During reception of a burst (bit DLR of the status register is 1), the DSP serial interface and associated
internal bus are dedicated to the transfer of RF data from the GSM baseband ADCs and DACs to the DSP.
During this period, only a write operation of internal registers can be done through the DSP serial interface.
However, all registers can be accessed by the MCU serial interface.
During transmission of a burst (bit ULX of the status register is 1), no read or write operation can be done
in the registers of the baseband uplink part of the GSM baseband, APC RAM, and APC shape register.
Writing or reading registers using the serial interface is done by transferring 16-bit words to the serial
interface. Each word is split into three fields as shown in Table 4–3.
Table 4–3. Read/Write Data Word
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^DATA
ADDRESS
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1/0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{When writing to internal registers observe the following convention:}
Bit 0:
This bit indicates a write operation at zero.
Bits 1 – 5: This field contains the address of the register to be accessed.
Bits 6 – 15: This field contains the data to be written into the internal register.
When reading from internal registers observe the following convention:
Bit 0:
At 1, this bit indicates a read operation.
Bits 1 – 5: This field contains the address of the register to be accessed.
Bits 6 – 15: This field is an irrelevant status in a read request operation.
4–17