TCM4400 Datasheet, PDF (31/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

3 Parameter Measurement Information
3.1 Uplink Timing Considerations
Figure 3–1 shows the timing diagram for the uplink operation.
Timing for power up, offset calibration, data transmission, and power ramp up are driven by control bits
applied to BULON (base uplink on), BCAL (calibration), and BENA (enable). The burst content including
guard bits, tail bits, and data bits, is sent by the DSP by way of the DSP interface and then stored by the
TCM4400 in a burst buffer. Transmission start is indicated by the control bit BENA when the BULON is
active. The transmission, sequencing, and power ramp up are then controlled by an on-chip burst sequencer
with a one-quarter-bit timing accuracy. For a detailed description of the baseband in-length path, see the
functional description of the baseband uplink path in the principles of operation section.
BULON
BCAL
tsu2
tw1
tsu3
th2
BENA
tw2
MODULATION
APC
tr1
th1
tsu1
tf1
th3
Figure 3–1. Uplink Timing Diagram
3–1