TCM4400 Datasheet, PDF (45/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

4.4.1 Voice Uplink Path
The voice uplink path includes two input stages (see Figure 4–9). The first is a microphone amplifier
compatible with an electret microphone containing an field-effect transistor (FET) buffer with open-drain
output. It has a gain of typically 27 dB and provides an external voltage of 2 V to 2.5 V to bias the microphone.
The auxiliary audio input can be used as an alternative source for a higher level speech signal. This stage
performs single-ended-to-differential conversion and provides a gain of 6 dB. When auxiliary audio input
is used, the microphone input is disabled and powered down. If both microphone and auxiliary amplifiers
are powered up at the same time, only the signal of the microphone amplifier is transmitted to the voice uplink
path.
The resulting fully differential signal is fed to a programmable gain amplifier that allows adjustment of the
level of the speech signal to the dynamic range of the ADC, which is determined by the value of the internal
voltage reference. Programmable gain can be set from –12 dB to 12 dB in 1-dB steps and is programmed
with bits VULPG to VULPG4 of the VBCTL1 register.
Analog-to-digital conversion is made with a third-order sigma-delta modulator whose sampling rate is 1
MHz. Output of the A/D converter is fed to a speech digital filter which performs the decimation down to 8
kHz and limits the band of the signal with both low-pass and high-pass transfer functions. The speech
samples are then transmitted to the DSP using the voice serial interface at a rate of 8 kHz.
Programmable functions of the voice uplink path, power up, input selection, and gain are controlled by the
DSP or the MCU using the serial interfaces. The uplink voice path can be powered down with the bit VULON
of the VBCTL1 internal register.
MICBIAS
MICIP
MICIN
AUXI
Bias
Generator
Microphone
Amplifier
27 dB
Auxiliary
Amplifier
6 dB
PGA
+ 16.6 – 7.4 dB
Sidetone
to Voice
Downlink
Sigma-Delta
Modulator
f_s1 = 1 MHz
SINC
Filter
f_s2 = 40 KHz
IIR
Band Pass
Filter
f_s3 = 8 kHz
To Voice
Serial Interface
Figure 4–9. Uplink Path Block Diagram
4.4.2 Voice Downlink Path
The voice downlink path receives speech samples at an 8-kHz rate from the voice serial interface and
converts them to analog signals to drive the external speech transducer.
The digital speech coming from the voice serial interface is first fed to a speech-digital infinite-duration
impulse response (IIR) filter, which has two functions (see Figure 4–10). The first function is to interpolate
the input signal and increase the sampling rate from 8 kHz up to 1 MHz to permit D/A conversion by an
oversampling digital modulator. The second function is to limit the band of the speech signal using both
low-pass and high-pass transfer functions.
The interpolated and band-limited signal is fed to a second-order sigma-delta modulator and sampled at 1
MHz to generate a 1-bit oversampled signal that drives a 1-bit DAC.
Due to the oversampling conversion, the analog signal obtained at the output of the one-bit DAC is mixed
with high frequency noise. This noise is filtered by a switched-capacitor third-order low-pass filter and the
remaining signal is fed to a programmable gain amplifier (PGA) to adjust the volume control. Volume control
is done in 6-dB steps from 0 dB through – 24 dB; in the mute state, attenuation is higher than 40 dB. A fine
adjustment of gain is possible from – 6 to 6 dB in 1-dB steps to calibrate the system, depending on the
earphone characteristics. This configuration is programmed using the VBCTL 2 register.
4–9