TCM4400 Datasheet, PDF (52/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

Table 4–2. Microcontroller Clocking Schemes
UPOL UPHA
MCU Clocking Scheme
1
1 Falling edge without delay
1
0 Falling edge with delay
0
1 Rising edge without delay
0
0 Rising edge with delay
4.10.3 DSP/MCU Serial Interface
The DSP/MCU serial interface not only configures the GSM baseboard and voice A/D and D/A conversion
but also transmits data to the DSP during downlink burst reactions. The following paragraphs describe the
operation of the serial interface in more detail.
4.10.4 DSP Serial Digital Interface
The DSP serial digital interface (see Figure 4–11) transfers the baseband transmit and receive data, and
also accesses all internal programming registers of the device (baseband codec, voice codec, and auxiliary
RF functions). The format for the serial interface is 16 bits.
The baseband serial digital interface is a bidirectional (transmit/receive) serial port. Both receive and
transmit operations are double buffered and permit a continuous communication stream (16-bit data
packets). The serial port is fully static and functions with any arbitrary, low clocking frequency.
Six terminals are used for the serial port interface (see Figure 3–4 for timing diagram). BCLKR is an I/O port
for the serial clock used to control the reception of the data BDR. At reset BCLKR is configured as an output
and the clock frequency is set to MCLK/3 (4.333 MHz with MCLK = 13 MHz); the clock signal is running
continuously. The port BCLKR can be reconfigured as an input by programming an internal register. In this
case BCLKR is provided by the DSP and can run in burst mode to reduce power consumption. The receive
frame synchronization (BFSR) is used to identify the beginning of a data packet transfer on port BDR.
The transmitted serial data (BDX) is the serial data input; the transmit frame synchronization (BFSX) initiates
the transmission of data. The transmit clock (BCLKX) is provided by the GSM baseband and voice ADCs
and DACs with a MCLK frequency. The clock signal BCLKX can run in burst mode or continuous mode,
depending on the BCLKMODE bit. The downlink data bus (BFSX, BCLKX, BDX) can be driven to V_SS or
placed in a high-impedance state when no data is to be transferred to the DSP. The BCLKDIR bit of the
BCTLREG register controls the direction of the BCLKR clock.
As with the voice serial interface, one extra clock cycle must be generated because the last 16-bit word
received on the DSP serial interface is latched on the next two falling BCLKR edges following the LSB. As
for the voice serial interface, one extra clock period is generated on the BCLKX before the first
synchronization BFSX of the downlink data sequence.
4–16