TCM4400 Datasheet, PDF (35/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

3.5 Voice Band Serial Interface Timing Considerations
Figure 3–5 shows the timing diagram for both transmit and receive voice band serial interface operation.
The signal VCLK is the output serial clock used to control the transmission or reception of the data. The
transmitted serial data (VDX) is the serial data output; the frame synchronization (VFS) initiates the transfer
of transmit and receive data. The received data (VDR) is the serial data input.
Each serial port includes four registers: the data transmit register (DXR), the data receive register (DRR),
the transmit shift register (XSR), and the receive shift register (RSR).
The voice serial interface has the same structure and timing diagram as the serial interface; one extra cycle
is generated before VFS and two extra cycles are generated after the LSB.
XLOAD and RLOAD are internal signals.
VCLK
tsu7
tsu8
th6
th8
VFS
VDX
XLOAD
A15 A14 A13 A12
MSB
A3
A2
A1
A0
LSB
DXR
Loaded
VCLK
XSR
Loaded
VFS
a. Audio-Serial-Port Transmit Operation
tsu9
th7
VDR
RLOAD
A15 A14 A13 A12
MSB
A3
A2
A1
A0
LSB
b. Audio-Serial-Port Receive Operation
Figure 3–5. Voice Band Serial Interface Timing Waveforms
DDR
Loaded
3–5