TCM4400 Datasheet, PDF (34/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

3.4 DSP Serial Port Timing Considerations
Figure 3–4 shows the timing diagram for DSP serial port operation.
Six terminals are used for the serial port interface. The terminal BCLKR is an I/O port for the serial clock used
to control the reception of the data BDR. At reset BCLKR is configured as an output and the clock frequency
is set to MCLK/3 (4.333 MHz with MCLK = 13 MHz); the clock signal is running permanently. The port BCLKR
can be reconfigured as an input by programming an internal register. In this case BCLKR is provided by the
DSP and can run in burst mode to reduce power consumption. The receive frame synchronization (BFSR)
identifies the beginning of a data packet transfer on port BDR.
The transmitted serial data (BDX) is the serial data input; the transmit frame synchronization (BFSX) initiates
the transmission of data. The transmit clock (BCLKX) is provided by the GSM baseband and voice A/D and
D/A converters with a frequency of MCLK. The downlink data bus (BFSX, BCLKX, BDX) can be driven to
V_SS or placed in high-impedance state when no data is to be transferred to the DSP. The bit BCLKDIR of
the register BCTLREG controls the direction of the BCLKR clock.
As with the voice serial interface, an extra clock cycle must be generated because the last 16-bit word
received on the DSP serial interface is latched on the next two falling BCLKR edges, following the least
significant bit (LSB). As for the voice serial interface, one extra clock period is generated on the BCLKX
before the first synchronization BFSX of downlink data sequence.
BCLKX
tsu12
BFSX
tsu13
th13
th14
BDX
BCLKR
tsu14
BFSR
A15
MSB
A14 A13 A12
A3 A2 A1
a. Burst-Mode Serial-Port Transmit Operation
A0
LSB
tsu15
th14
th15
BDR
A15 A14 A13 A12
A3
A2 A1
A0 B15 B14 B13
MSB
LSB
b. Burst-Mode Serial-Port Receive Operation
Figure 3–4. DSP Serial Port Timings
3–4