TCM4400 Datasheet, PDF (29/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

2.13.3
tsu10
tv1
tv2
th9
th10
th11
tsu11
th12
tc
MCU Serial Interface Timing Requirements (See Figure 3–3)
MIN NOM
Setup time, UCLK stable before USEL↓
20
Hold time, UDX valid after USEL↓
Hold time, UDX valid after UCLK↑
Sequential transfer delay between 16-bit word acquisition tw pulse
duration, USEL high
3000
Hold time, UCLK↑ after USEL↓
20
Hold time, UCLK unknown after USEL↑
20
Setup time, data valid before UCLK↓
20
Hold time, data valid after UCLK↓
20
Cycle time, ULCK
154
MAX
20
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.13.4 DSP Serial Interface Timing Requirements (See Figure 3–4)
MIN
BCLKX BCLKX signal frequency (burst mode or continuous mode depending
on bit BCLKMODE)
BCLKX BCLKX duty cycle
45
tsu12 Setup time, BFSX high before BCLKX ↓
20
th12
Hold time, BFSX high after BCLKX ↓
20
tsu13 Setup time, BDX valid before BCLKX ↓
20
th13
Hold time, BDX valid after BCLKX ↓
20
BCLKR BCLKR signal frequency
(Output BCLKDIR = 0)
(Input BCLKDIR = 1)
BCLKR BCLKR duty cycle
45
tsu14 Setup time, BFSR high before BCLKR ↓
20
th14
Hold time, BFSR high after BCLKR ↓
20
tsu16 Setup time, BDR valid before BCLKR ↓
20
th15
Setup time, BDR valid after BCLKR ↓
20
NOM
13
50
4.33
50
MAX
55
13
55
UNIT
MHz
%
ns
ns
ns
ns
MHz
%
ns
ns
ns
ns
2.13.5 Voice Timing Requirements (See Figure 3–5)
VCLK
VCLK
tsu7
th6
tsu8
th8
tsu9
th7
VCLK signal frequency (burst mode or continuous mode depending
on bit VCLKMODE)
VCLK duty cycle
Setup time, VFS high before VCLK ↓
Hold time, VFS high after VCLK ↓
Setup time, VDX valid before VCLK ↓
Hold time, VDX valid after VCLK ↓
Setup time, VDR valid before VCLK ↓
Hold time, VDR valid after VCLK ↓
MIN NOM MAX UNIT
520
kHz
45
50
55 %
100
ns
100
ns
100
ns
100
ns
100
ns
100
ns
2–15