TCM4400 Datasheet, PDF (32/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

3.2 Downlink Timing Considerations
Figure 3–2 shows the timing diagram for downlink operation.
Timing of the baseband downlink path is controlled by bits DLON (downlink on), BCAL (calibration), and
BENA (enable) when BDLON is active (see the topic, timing and interface). BDLON controls the power up
of the baseband downlink path; BCAL controls the start and duration of the autocalibration sequence; and
BENA controls the beginning and the duration of data transmission to the DSP using the DSP serial
interface.
The power-down sequence is controlled with two bits. The first bit (BBDLW of PWDNRG1 register)
determines whether the baseband downlink path can be powered down with external GSM receive window
activation (BDLON); the second bit (BBDLPD of PWDNRG1 register) controls the activation of the
baseband downlink path. For more information about power down control, see Section 4.8 in this document.
BDLON
BCAL
tsu4
tw3
tsu5
th5
BENA
tw4
DATAOUT
tsu6
th4
Figure 3–2. Downlink Timing Sequence
3–2