TCM4400 Datasheet, PDF (50/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

VCLK is the output serial clock used to control the transmission or reception of the data, (see Figure 3–5).
VCLK can run in burst mode or continuous mode, depending on the VCLKMODE bit. The transmitted serial
data (VDX) is the serial data output; the frame synchronization (VFS) initiates the transfer of transmit and
receive data. The received data (VDR) is the serial data input.
Each serial port includes four registers: the data transmit register (DXR), the data receive register (DRR),
the transmit shift register (XSR), and the receive shift register (RSR).
The voice serial interface has the same structure and timing diagram as the serial interface. One extra cycle
is generated before VFS, and two extra cycles are generated after the least significant bit (see Figure 3–5).
4.10 Voltage References
Voltage and current generators are integrated inside the GSM converter. Some additional components are
required for the decoupling and regulation of the internal references. In addition, the internal buffers are
automatically shut down with the corresponding functions being powered down.
The following six terminals are reserved for voltage references decoupling and use: VGAP, IBIAS, VREF,
MICBIAS, and VMID (see Table 4–1):
VGAP:
This terminal is connected to the internal band gap reference voltage. It must be externally
connected to a 0.1-µF capacitor. The band gap drives the current generator and the voltage
reference. This band gap may be powered down by the PWRDN pin, depending on bit
VGAPPN of register PWDNRG2.
IBIAS:
This terminal is connected to the current reference. It must be externally connected to a
100-kΩ resistor. Because this block is connected to the AFC function, the power down is
controlled by similar means. The current generator is shut down with the same bits of the
band gap: one bit for the power down selection of a hardware solution (with the external
PWRDN terminal).
VREF:
This terminal is connected to the internal reference voltage. It must be externally connected
to a 0.1-µF capacitor. This band gap may be down powered under the control of bits VREFPN
and VREFPD of register PWDNRG2. This voltage reference is internally connected to three
buffers corresponding to the blocks of speech downlink, speech uplink, and GMSK downlink.
The two first blocks are powered down with the inactivity of the corresponding speech
blocks. This last block is shut down outside the radio downlink activations.
VMID: This buffer gives the V_DD/2- or 1.35-V common-mode output voltage of the baseband uplink
path. This voltage value is selected with the SELVMID bit.
MICBIAS: This buffer is destined to drive an electret-type microphone. The output voltage can be
chosen by software (bit MICBIAS of the VBCTL1 register) from 2 V to 2.5 V.
ADCMID: For decoupling purposes, the ADCMID terminal is connected to the internal comparison
threshold of the ADC. Setup time before the ADC is powered on depends on the value of the
external decoupling capacitor.
REFERENCE
VGAP
VREF
VMID
MICBIAS
ADCMID
VOLTAGE
1.22 V
1.75 V
AVDD2/2
2 V/2.5 V
AVDD3 /2
Table 4–1. Voltage References
DEFINITION
Band gap used for all other references
Voltage reference of GMSK internal ADC and DAC
Common-mode reference for uplink/downlink GMSK
Microphone-driving voltage
Voltage dc biasing of the auxiliary ADCs
4–14