TCM4400 Datasheet, PDF (54/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

Read operation from the downlink baseband codec is done using the TX part of the DSP/MCU serial
interface in the 16-bit word format defined in Table 4–4.
Table 4–4. 16-Bit Word Format
DATA
ADDRESS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{15 14 13 12 11 10 9 8 7 6}
5
4
3
2
1
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A4}
A3
A2
A1
A0
0
During reception of a burst, transfer of RF data from the downlink baseband codec is done using the transmit
part of the DSP serial interface in the 16-bit word format, defined in Table 4–5. Because the I and Q samples
are coded with 16-bit words, the data rate is 270833 × 16 × 2, which equals 8.66 Mbps. I and Q samples
are differentiated by setting the LSB to zero for I samples and to one for Q samples. Because the digital clock
MCLK is 13 MHz, transfer is done at 13 Mbps in burst mode. During burst reception, the DSP serial interface
is idle about 33 percent of the time.
Table 4–5. Format of 16-Bit Word Transfer
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DATA
I/Q
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1}
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1}
D0
4.10.6 DSP/MCU Serial Interface Registers
The following internal register buffers are accessed using the DSP/MCU serial interface during manual
operation of the TCM4400.
4.10.7 Baseband Uplink Ramp-delay Register
Each bit position of the baseband uplink ramp-delay register is defined in Table 4–6.
Table 4–6. Uplink Ramp-Delay Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{BULRUDEL: BASEBAND UPLINK RAMP-DELAY REGISTER}
ADDRESS: 1 R/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{RESERVD IBUFPTR DELD DELD DELD DELD DELU DELU DELU DELU 0 0 0 0 1 1 / 0}
3
2
1
0
3
2
1
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{R = 0}
R/W
R/W R/W R/W R/W R/W R/W R/W R/W ←ACCESS TYPE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
0
0
0
0
0
0
0
0 ←VALUE AT RESET
DELU0 to DELU3: Value of the delay of ramp-up start versus the rising edge of BENA
DELD0 to DELD3: Value of the delay of ramp-down start versus the falling edge of BENA
IBUFPTR:
Writing a 1 in this bit initializes the pointer of the burst buffer to the base
address. This is not a toggle bit and has to be set back to 0 to allow writing
into the burst buffer.
RESERVD:
Reserved bits for testing purposes
R/W:
A 1 indicates a read operation; a 0 indicates a write operation.
4–18