TCM4400 Datasheet, PDF (65/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

4.11 Automatic Frequency Control Registers (1 and 2)
The content of the APC RAM describes the shape of the ramp-up and ramp-down control; as defined in
Table 4–29.
Table 4–29. APC Ramp Control
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{APCRAM: AUTOMATIC POWER CONTROL RAM}
ADDRESS: 17 (64 Words)
W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{RDWN WORD0 (5 BIT)}
RUP WORD0 (5 BIT)
1
0
0
0
1
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{RDWNWORD1 (5 BIT)}
RUP WORD1 (5 BIT)
1
0
0
0
1
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{RDWNWORD2 TO 61 (5 BIT) RUP WORD2 TO 61 (5 BIT)}
1
0
0
0
1
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{RDWNWORD62 (5 BIT)}
RUP WORD 62 (5 BIT)
1
0
0
0
1
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{RDWNWORD63 (5 BIT)}
RUP WORD 63 (5 BIT)
1
0
0
0
1
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ W W W W W W W W W W
←ACCESS TYPE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{X X X X X X X X X X}
←VALUE AT RESET
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Actual shape values (five bits long) are contained in the shape DAC input register, as defined in Table 4–30.
Table 4–30. Shape DAC Input Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ APCSHAP: SHAPE DAC INPUT REGISTER
ADDRESS: 18
R/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{RE RE RE RE RE BIT4 BIT3 BIT2 BIT1 BIT0 1 0 0 1 0}
1/0
ÁÁÁÁÁ _{SRVD SRVD SRVD SRVD SRVD}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{R = 0 R = 0 R = 0 R = 0 R = 0 R/W R/W R/W R/W R/W}
←ACCESS TYPE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
0
0
0
0
0
0
0
0
←VALUE AT RESET
Bits 4 – 0: Input of the 5-bit APC DAC
RESERVD: Reserved bits for testing
4.11.1 AGC Control Register
The AGC control register is 10 bits wide and controls operations of the analog AGC circuit, as defined in
Table 4–31.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _BIT9
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _R/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
Table 4–31. Analog AGC Gain Control Register
AUXAGC: AUTOMATIC GAIN CONTROL REGISTER
ADDRESS: 19
R/W
BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 1 0 0 1 1
1/0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
←ACCESS TYPE
0
0
0
0
0
0
0
0
0
←VALUE AT RESET
Bits 9 – 0: Input of the 10-bit AAGC DAC
RESERVD: Reserved bits for testing
4.11.2 Auxiliary Functions Control Register 2
The values in the auxiliary function control register 2 set the operation parameters as defined in Table 4–32.
AFCZ:
This bit selects the internal resistance of the AFC driver. When AFCZ is 1, the
resistance is 50 kΩ. When AFZ is 0, the resistance is 25 kΩ. The largest swing is
obtained with 50 kΩ.
APCSPD:
When this bit is cleared to 0, the APC clock is at 4 MHz; when set to 1, the APC
clock is at 2 MHz.
AGCSWG: This bit selects the swing of the AGC output: 0 corresponds to a 0-V to 2.0-V
swing; 1 corresponds to 0-V to 4-V swing.
4–29