TCM4400 Datasheet, PDF (58/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

4.10.12 Power-Down Register No. 1
The values in each bit position of power-down register 1 are defined in Table 4–13.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SEL
VMID
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _R/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
Table 4–13. PWDNRG1 Register
PWDNRG1: REGISTER FOR POWERING DOWN
BA VMID VMID BBUL BBUL BBDL BBDL EXT BBR
LOOP W PD
W
PD
W
PD CAL ST
R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
ADDRESS: 7
R/W
00111
1/0
←ACCESS TYPE
←VALUE AT RESET
BBRST: This is the digital reset of the baseband codec (active at 1); the uplink burst buffer is
loaded with all 1s, and the memory and registers of the downlink digital filter is
cleared to 0. This is not a toggle bit; it has to be set to 0 to remove the reset condition.
EXTCAL: Downlink autocalibration mode (0 = autocalibration; 1 = external calibration)
BBULW:
If this bit is cleared to 0, the baseband uplink path is powered down under the control
of the GSM transmit window (BULON terminal). If this bit is set to 1, the power down is
controlled only by bit BBULPD.
BBULPD: This bit is functionally associated with bit BBULW. When this bit is set to 1, the
baseband uplink path is in power-down mode.
BBDLW:
If this bit is cleared to 0, the baseband downlink path is powered down under the
control of the GSM receive window (BDLON terminal). If this bit is set to 1, the power
down is controlled only by bit BBDLPD.
BBDLPD: This bit is functionally associated with bit BBDLW. When this bit is set to 1, the
baseband downlink path is in power-down mode.
VMIDW:
If this bit is cleared to 0, the VMID output driver is powered down under the control of
the GSM transmit window (BULON terminal). If this bit is set to 1, the power down is
controlled only by bit VMIDPD.
VMIDPD: This bit is functionally associated with and paired with bit VMIDW. When VMIDW bit
is set to 1, the VMID output driver is active. When VMIDPD bit is set to 1, the VMID
output driver is in power-down mode.
BALOOP: When this bit is set to 1, the internal analog loop of I and Q uplink terminals are
connected to I and Q downlink terminals.
SELVMID: When this bit is cleared to 0, this sets the common-mode voltage of the baseband
uplink and VMID at V_DD/2; when set to 1, these voltages are set to 1.35 V.
4.10.13 Baseband Control Register
The values in the baseband control register bit positions determine whether the data is shifted left or right
(see Table 4–14). Note that the MCU clocking scheme determines the edge of the clock on which that data
is received or transmitted using the serial interface (see Table 4–15).
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RE-
SERVD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{R = 0}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
Table 4–14. Baseband Control Register
BCTLREG: BASEBAND CONTROL REGISTER
ADDRESS: 9 R/W
RE-
RE- MCL BCLK BIZ- BCL UDIR UPHA UPOL 0 1 0 0 1 1/0
SERVD SERVD KBP MODE BUS KDIR
R=0
R = 0 R /W R /W R/W R/W R/W R/W R/W ←ACCESS TYPE
0
0
0
0
0
0
0
0
0 ←VALUE AT RESET
4–22