TCM4400 Datasheet, PDF (59/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

UDIR:
This bit determines whether the data is shifted in from right (see serial register
description) to left, MSB first (bit value 0), or from left to right, LSB first (bit value 1).
BCLKMODE: When this bit is cleared to 0, BLCKX runs in burst mode; when set to 1, BCLKX is
continuous.
MCLKBP:
When this bit is cleared to 0, the MCLK signal passes through the clock slicer;
when set to 1, the clock slicer is bypassed (in this case, the signal at the MCLK
terminal must be digital).
4.10.14 MCU Clocking Schemes
Falling edge without delay: The MCU serial interface transmits data on the falling edge of UCLK
and receives data on the rising edge of UCLK.
Falling edge with delay: The MCU serial interface transmits data one half-cycle ahead of the
falling edge of UCLK and receives data on the falling edge of UCLK.
Rising edge without delay: The MCU serial interface transmits data on the rising edge of UCLK
and receives data on the falling edge of UCLK.
Rising edge with delay: The MCU serial interface transmits data one half-cycle ahead of the
rising edge of the UCLK and receives data on the rising edge of
UCLK.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _UPOL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
Table 4–15. MCU Clocking Schemes
UPHA
MCU CLOCKING SCHEME
1 Falling edge without delay
0 Falling edge with delay
1 Rising edge without delay
0 Rising edge with delay
BCLKDIR: Direction of the BCLKR port ( 0 → Output, 1 → Input).
BIZBUS:
When this bit is set to 1, BDX, BCLKX, BFSX are in hi-Z when there is nothing to
transfer to the DSP; when it is cleared to 0, DBX, BCLKX, and BFSX are set to V_SS
when there is nothing to transfer to the DSP.
RESRVD: Bits are reserved for testing purpose.
4.10.15 Voice Band Uplink Control Register
The values in the voice band uplink control register bit positions control not only the power level of the audio
in the uplink path but also set the gain of the PGA from –12 dB to 12 dB in 1-dB steps. Bit MICBIAS and
VULMIC and VULAUX are shifted by one position to the left. This is defined in Table 4–16.
Table 4–16. Voice Band Uplink Control Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ VBCTL1: VOICE BAND UPLINK CONTROL REGISTER
ADDRESS: 10 R/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{RESERVD MIC- VUL VUL VUL VUL VUL VUL VUL VULON 0 1 0 1 0}
1/0
BIAS MIC AUX PG4 PG3 PG2 PG1 PG0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{R = 0}
R /W R/W R/W R/W R/W R/W R/W R/W R/W
←ACCESS TYPE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
0
0
0
0
0
0
0
0
←VALUE AT RESET
4–23