TCM4400 Datasheet, PDF (68/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

4.11.6 Baseband Uplink Register (Address 24)
The baseband uplink register (BULCTL) is a 3-bit register (see Table 4–37) that permits mismatch
compensation in the RF transmit mixer. Gain mismatches of 0 dB, – 0.25 dB, – 0.5 dB, and – 0.75 dB are
permitted between the I and Q channel, as defined in Table 4–38.
Table 4–37. Uplink Register BULCTL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{BULCTL: BASEBAND UPLINK CONTROL REGISTER}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{RE RE RE RE RE RE RE IQSEL G1 G0}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{SRVD SRVD SRVD SRVD SRVD SRVD SRVD}
R = 0 R = 0 R = 0 R = 0 R = 0 R = 0 R = 0 R/W R/W R/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
0
0
0
0
0
0
0
0
ADDRESS: 24
R/W
11000
1/0
←ACCESS TYPE
←VALUE AT RESET
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BIT2
IQSEL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
1
Table 4–38. BLKCTL Register
BIT1
G1
BIT0
G0
GAIN I
0
0
0 dB
0
1
– 0.25 dB
1
0
– 0.50 dB
1
1
– 0.75 dB
0
0
0 dB
0
1
0 dB
1
0
0 dB
1
1
0 dB
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{4.11.7 Power-On Status Register (Address 25)}
GAIN Q
0 dB
0 dB
0 dB
0 dB
0 dB
– 0.25 dB
– 0.50 dB
– 0.75 dB
The power-on status register is a 9-bit, read-only register which displays the status power-on/power down
of the functions having several power on/off controls as defined in Table 4–39. When the function is in
power-on status, the corresponding bit is at 1.
Table 4–39. Power-On Status Register PWONCTL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RESRVD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ R = 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ⁰
PWONCTL: POWER-ON STATUS REGISTER
BGA VREF BBIF TIMIF VMID AFC ADC
P ON ON ON ON ON ON ON
R
R
R
R
R
R
R
0
0
0
0
0
0
0
AGC
ON
R
0
APC
ON
R
0
ADDRESS: 25 R/W
1 1 0 0 1 1/0
←ACCESS TYPE
←VALUE AT RESET
(See Note 1)
NOTE 1: PWONCTL is the power-on status register value at reset when the PWRDN terminal is set high.
4.11.8 Timing and Interface
Accurate timing control of baseband uplink and downlink paths is performed using the timing serial interface.
The timing interface is a parallel asynchronous port with four control signals (see Figure 4–12). The BDLON
bit controls power on the downlink path of the baseband codec; the BULON bit controls power on the uplink
path of the baseband codec; and the BCAL bit controls the calibration of the active parts of the baseband
codec selected by BULON or BDLON.
The BENA bit controls the transmission of the reception of burst, depending on which part of the baseband
codec is selected by the signals BULON or BDLON. These asynchronous inputs are internally synchronized
with the uplink and downlink internal clocks and stored in timing register TR. The timing register, TR, is a
6-bit register containing the bits defined in Table 4–40.
4–32