TCM4400 Datasheet, PDF (51/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

4.10.1 MCU Serial Baseband Digital Interface
The GSM baseband and voice A/D and D/A conversion provide two digital serial 16-bit interfaces for use
with the DSP and a microcontroller device. Through this interface, a microcontroller can access all the
internal registers that can be accessed through the DSP digital serial interface.
This option is for applications in which part of layer-1 software is implemented into the microcontroller and
needs access to some functions implemented into the GSM baseband and voice A/D and D/A conversion
circuitry.
4.10.2 Serial Interface
The microcontroller serial interface is compliant with 8-bit standard synchronous serial ports. This interface
consists of four terminals (see Figure 3–4 for timing diagram).
UCLK: A clock provided by the microcontroller to GSM baseband and voice A/D and D/A conversion
UDR: An input terminal of the GSM baseband and voice A/D and D/A components for reception of
data
UDX: An output terminal of the GSM baseband and voice A/D and D/A components for
transmission of data
USEL: An input terminal of GSM baseband and voice A/D and D/A components for activation of the
serial interface
When USEL = V_DD, the serial interface is deactivated and UDX is placed in a high-impedance state. A high
level on USEL resets the internal serial interface; the 16-bit transfers must be completed with USEL = V_SS.
The external MCU initiates data transfer by driving the selection terminal and sending a clock signal. For
both the GSM baseband and voice A/D and D/A components, the MCU data is shifted out of the shift
registers on one edge of the clock and latched into the shift registers on the opposite clock edge.
As a result, both controllers send and receive data simultaneously. For the MCU portion, the software
determines whether the data is meaningful or dummy data. On the GSM baseband and voice A/D and D/A
conversion portion, dummy data is data with all zeroes.
The 16-bit word data format is identical to the DSP data format. After a read-register command, there is a
sequential transfer delay between two 16-bit word acquisitions to let the internal sequencer extract the data
going from internal registers to the serial shift register.
Three internal bits control the data serial flow as follows:
• UDIR determines whether data is transferred with MSB or LSB first.
• UPOL determines the polarity of the clock.
• UPHA determines the insertion of a half-clock period in the data serial flow.
With UPOL and UPHA, there are four clock schemes (see Table 4–2):
• Falling edge without delay. The MCU serial interface transmits data on the falling edge of the
UCLK and receives data on the rising edge of the UCLK.
• Falling edge with delay. The MCU serial interface transmits data one half-cycle ahead of the
falling edge of the UCLK and receives data on the falling edge of the UCLK.
• Rising edge without delay. The MCU serial interface transmits data on the rising edge of the
UCLK and receives data on the falling edge of the UCLK.
• Rising edge with delay. The MCU serial interface transmits data one half-cycle ahead of the
rising edge of the UCLK and receives data on the rising edge of the UCLK.
4–15