TCM4400 Datasheet, PDF (18/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

2.3.9 Baseband Uplink Path Global Characteristics
PARAMETER
GMSK phase trajectory error
Power supply rejection
MIN TYP MAX UNIT
6° peak
1.5° rms
46
dB
2.4 Timing Requirements of Baseband Uplink Path
2.4.1 Programmable Delays – Baseband Uplink Path (See Figure 3–1)
MIN NOM
tsu1 Setup time, BENA↑ before APC↑
Bits DELU of register BULRUDEL
0
th1
Hold time, ramp-down from BENA
low
Bits DELD of register BULRUDEL
0
Bit APCSPD = 0
tr, tf Transition time, APC
Bit APCSPD = 1
0
MAX UNIT†
15 1/4-bit
15 1/4-bit
1/16-bit
64
1/8-bit
2.4.2 Fixed Delays – Baseband Uplink Path (See Figure 3–1)
MIN NOM MAX UNIT†
tsu2
Setup time, BULON↑ to BCAL↑
15
tw1
Pulse duration, BCAL high
132
tsu3
Setup time, BCAL low before BENA↑
0
tw2
Pulse duration, BENA high
N effective duration of burst
controlled by BENA
N– 32
µs
µs
µs
1/4-bit
th2
Hold time, modulation low after
BENA low
32
bit
th3
Hold time, BULON↓ after APC low
1
bit
tdd(mod) Input-to-output modulator delay
Digital delay of modulator
1.5
bit
† _{Bit is relative to GSM bit = 1/270 kHz. Units can be a fractional part of the GSM bit as noted. Values in the above table}
are given for system information only.
2.4.3 Baseband Downlink Path
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Dynamic range on each input
Centered on external common
mode (VBDLCOM)
VVREF
Vpp
Differential input dynamic range
DLQP–DLQN or DLIP–DLIN
2 × VVREF
Vpp
Differential input resistance at
BDLQP–BDLQN or BDLIP–BDLIN
130
200
270
kΩ
Differential input capacitance at
BDLQP–BDLQN or BDLIP–BDLIN
1.5
4
6.5
pF
Single-ended input resistance at
BDLQP or BDLQN or BDLIP or BDLIN
to ground
90
130
180
kΩ
Single-ended input capacitance at
BDLQP or BDLQN or BDLIP or BDLIN
to ground
6
8
12
pF
External common-mode input voltage:
VBDLCOM
Range of digital output data
Maximum digital code value
on 16-bit I and Q samples
0.8 VDD /2 VDD – 0.8 V
± 21060
2–4