TCM4400 Datasheet, PDF (66/72 Pages) Texas Instruments – GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT

APCSWG: This bit selects the swing of the APC output: 0 corresponds to a 0-V to 2-V swing; 1
corresponds to 0-V to 4-V swing.
IAPCPTR:
Setting this bit to 1 initializes the pointer of the APC RAM to the base address. This
is not a toggle bit and has to be set to 0 to set APC RAM operational.
APCMODE: This bit selects the equation used for APC waveform generation.
AGCW:
If this bit is cleared to 0, the automatic gain control path is powered down with the
control of the GSM receive window (BDLON terminal) and the AGCPD bit. If the
AGCPD bit is set to 1, the power down is controlled by the AGCPD bit.
AGCPD:
This bit is functionally associated with the AGCW bit. When this bit is set to 1, the
automatic gain control path is in power-down mode.
APCW:
If this bit is 0, the RF power control path is down powered with the control of the
GSM transmit window (BULON) and with the control of the APCPD bit. If the
APCPD bit is set to 1, power down is controlled only by the APCPD bit.
APCPD:
This bit is functionally associated with the BBULW bit. When this bit is set to 1, the
RF power control path is in power-down mode.
Table 4–32. AUX Functions Control Register 2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{AUXCTL2: AUXILIARY FUNCTIONS CONTROL REGISTER 2}
ADDRESS: 20 R/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ AGCW AGCPD APCW APC IAP APC APC AGC APC AFCZ 1 0 1 0 0 1/0
PD CTR MODE SWG SWG SPD
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W}
←ACCESS TYPE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
0
0
0
0
0
0
0
0
←VALUE AT RESET
4.11.3 Auxiliary A/D Converter Output Register
This register is read-only; however, if there is an attempt to write to it, an A/D conversion operation starts;
see Table 4–33. When the A/D conversion is finished, the AUXADC register is loaded and the ADC is
automatically powered down. During the conversion process, the ADCEOC bit of the BSTATUS register is
set. This bit is reset automatically after AUXADC is loaded.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _BIT9
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _R/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
Table 4–33. AUX A/D Converter Output Register
AUXADC: AUXILIARY A/D CONVERTER OUTPUT REGISTER
BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
0
0
ADDRESS: 21 R
1 0 1 0 1 1/0
←ACCESS TYPE
←VALUE AT RESET
Bits 9 – 0: Output of the 10-bit monitoring ADC
4.11.4 Baseband Status Register
The baseband status register stores the baseband status as defined in Table 4–34.
Table 4–34. Baseband Status Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ BSTATUS: BASEBAND STATUS REGISTER
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{RESERVD ADCEOC RAM BUF UL UL ULX DL DL}
PTR PTR ON CAL
ON CAL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{R = 0}
R
R
R
R
R
R
R
R
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
1
1
0
0
0
0
0
ADDRESS: 22 R
DLR 1 0 1 1 0 1
R
←ACCESS TYPE
0 ←VALUE AT RESET
DLR:
This bit is set to 1 during conversion of a burst in the downlink path.
4–30