TLK3114SA_13 Datasheet, PDF (60/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

4.7 HSTL Signals
See Chapter 2, Terminal Descriptions, for a list of HSTL signals.
NOTE: For more information on HSTL specifications and test conditions, see the EIA/JEDEC,
High-Speed Transceiver Logic (HSTL): A 1.5-V Output Buffer Supply Voltage Based Interface
Standard for Digital Integrated Circuits, EIA/JESD8-6, Aug 1995.
VOH(dc)
VOL(dc)
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
IOH(dc)
IOL(dc)
CIN
PARAMETER
High-level output voltage
Low-level output voltage
High-level dc input voltage
Low-level dc input voltage
High-level ac input voltage
Low-level ac input voltage
High-output current
Low-output current
Input capacitance
TEST CONDITION
DC input, logic high
DC input, logic low
AC input, logic high
AC input, logic low
VDDQ = 1.5 V
VDDQ = 1.5 V
MIN
VDDQ−0.4
Vref+0.1
−0.3
Vref+0.2
−8
8
TYP
MAX UNIT
VDDQ
V
0.4 V
VDDQ+0.3
V
Vref–0.1
V
V
Vref–0.2
V
mA
mA
4 pF
4.8 Serial Transmitter/Receiver Characteristics
VOD(p)
VOD(d)
PARAMETER
TX output voltage magnitude away from common
mode
VOD(pp)
VOD(pd)
TX output differential peak-to-peak voltage swing
VCMT
VID
VID(p)
VCMR
ILKG
CI
TX output common-mode voltage range
RX input voltage magnitude away from common
mode
RX input differential peak-to-peak voltage swing
RX input common-mode voltage range
RX input leakage current
RX input capacitance
tr, tf
Differential output signal rise, fall time (20% to 80%)
JTOL
JDR
JS
Jitter tolerance, total jitter at serial input
Serial input deterministic jitter
Serial input sinusoidal jitter <20 MHz
JT
Serial output total jitter
JD
Serial output deterministic jitter
R(LATENCY) Total delay from RX input to RD output
T(LATENCY) Total delay from TD input to TX output
† _{Unit interval (UI) is one serial bit time (320 ps minimum).}
TEST CONDITION
Maximum preemphasis
enabled, See Figure 4−1
Preemphasis disabled,
See Figure 4−1
Maximum preemphasis
enabled, See Figure 4−1
Preemphasis disabled,
See Figure 4−1
See Figure 4−1
See Figure 4−3
See Figure 4−3
See Figure 4−3
RL = 50 Ω, CL = 5 pF,
See Figure 4−1
Zero crossing, See Figure 4−4
Zero crossing, See Figure 4−4
PRBS at 3.125 GHz,
See Figure 4−2
PRBS at 3.125 GHz
See Figure 3−6
See Figure 3−2
MIN TYP MAX UNIT
650 850 1000 mV
600
800 mV
1300 1700 2000 mV_P-P
1200 1450 1600 mV_P-P
1000 1250 1400 mV
100
1150 mV
200
1000
−10
2300 mV_P-P
2000 mV
10 µA
2 pF
80
90 130 ps
0.65 UI†
0.37 UI
0.1 UI
0.2 0.35 UI
0.17 UI
89
225 Bits
71
120 Bits
4−3