TLK3114SA_13 Datasheet, PDF (55/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

Table 3−42. 10G DTE XS Status 2 Register (Register 5.8)
BIT(S)
15
14
13:12
NAME
Device present
Device present
Reserved
11
Transmit local fault
10
Receive local fault
9:0
Reserved
DESCRIPTION
Read returns 1.
Read returns 0.
Read is ignored.
1 = Transmit fault detected
0 = No transmit fault detected
Latches high until read.
1 = Receive fault detected
0 = No receive fault detected
Latches high until read.
Read is ignored.
READ/WRITE
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Table 3−43. 10G DTE XGXS Lane Status Register (Register 5.24)
BIT(S)
15:13
12
11:4
3
2
1
0
NAME
Reserved
Lane alignment
Reserved
Lane D sync
Lane C sync
Lane B sync
Lane A sync
DESCRIPTION
Read is ignored.
1 = DTE XGXS transmit lanes aligned
0 = DTE XGXS transmit lanes not aligned
Read is ignored.
Lane D is synchronized
Lane C is synchronized
Lane B is synchronized
Lane A is synchronized
READ/WRITE
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
MDIO registers 5.32768−5.32781 are analogous to registers 16−29. The following table cross references the
appropriate register definition.
Table 3−44. DTE XS Register Cross Reference (Registers 5.32768−5.32776)
REGISTER
ADDRESS
NAME
EQUIVALENT
REGISTER
ADDRESS
EQUIVALENT REGISTER
NAME
DEFINITION
5.32768
DTE XS global configuration
16
Global configuration
See Table 3−18
5.32769−5.32772 DTE XS channel A−D configuration
17−20
Channel A−D configuration
See Table 3−19, Table 3−20,
Table 3−21, and Table 3−22
5.32774
DTE XS channel status
22
Channel status
See Table 3−23
5.32775
DTE XS channel sync status
23
Channel sync status
See Table 3−24
5.32776
DTE XS CTC status
24
CTC status
See Table 3−25
5.32777
Error counter control
25
Error counter control
See Table 3−26
5.32778−5.32781 Channel A−D error count
26−29
Channel A−D error count
See Table 3−27, Table 3−28,
Table 3−29, and Table 3−30
3.26 Operating Frequency Range
The TLK3114SA device is optimized for operation at a serial data rate of 3.125 Gbps. The TLK3114SA device may
operate at a serial data rate between 2.5 Gbps to 3.125 Gbps. The external differential reference clock has an
operating frequency from 125 MHz to 156.25 MHz. The reference clock frequency must be within ±100 PPM and have
less than 40 ps of jitter.
3.27 Power-Down Mode
When the ENABLE terminal is held low, the TLK3114SA device enters a low power quiescent state. In this state, all
analog and digital circuitry is disabled. In the power-down mode, the serial transmit and the receive data bus terminals
for all channels are in a high-impedance state.
3−36