TLK3114SA_13 Datasheet, PDF (47/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

BIT(S)
15:12
11
10:9
8
7
6
5
4
3
2
1
0
Table 3−21. Channel C Configuration Registers Bit Definitions (Register 19)
NAME
DESCRIPTION
Reserved
Read returns all 0s, writes are ignored.
Clock tolerance
compensation
1 = Enable clock tolerance compensation.
0 = Disable clock tolerance compensation (default).
Logically ORed with register 16, bit 11.
Multifunction pin output
Multifunction (MFC) pin configuration for channel C.
Bit 10
0
0
1
1
Bit 9
0
1
0
1
MFC Output
HSTL = 1, SSTL_2 = 0 (default)
1 = Comma detected, 0 = data
Register 22, bit 2 (LOS)
Register 22, bit 6 (PRBS Pass)
Logically ORed with register 16, bits 10 and 9.
Loss of signal detection
1 = Enable LOS condition described in Table 3−7 for channel C (default).
0 = Disable this function.
Logically AND’ed with register 16, bit 8.
Configuration: Config1
Configuration bits (see Table 3−10), default value = 0
When CONFIG1 = low, this bit can be set to 1.
When CONFIG1 = high, this bit is read-only.
Logically ORed with register 16, bit 7.
Configuration: Config0
Configuration bits (see Table 3−10), default value = 0
When CONFIG0 = low, this bit can be set to 1.
When CONFIG0 = high, this bit is read-only.
Logically ORed with register 16, bit 6.
Preemphasis: Pre2
Programmable preemphasis control (see Table 3−9), default value = 0.
Logically ORed with register 16, bit 5.
Preemphasis: Pre1
Programmable preemphasis control (see Table 3−9), default value = 0.
Logically ORed with register 16, bit 4.
Loopback
1 = Enable loopback mode on channel C.
0 = Disable loopback mode on channel C (default).
Logically ORed with register 0, bit 14.
1 = Enable PRBS internal generation and verification on channel C.
0 = Normal operation (default).
PRBS enable
Logically ORed with register 16, bit 2
When PRBSEN = low, this bit can be set to 1.
When PRBSEN = high, this bit is read-only.
Comma detect enable
1 = Enable K28.5 code detection and bit alignment on channel C (default).
0 = Disable K28.5 code detection on channel C.
Logically AND’ed with SYNCEN and register 16, bit 1.
Power down
1 = Power-down mode is enabled for channel C.
0 = Normal operation (default).
Logically ORed with register 0, bit 11.
READ/WRITE
Read-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
3−28