TLK3114SA_13 Datasheet, PDF (39/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

Result reporting of the PRBS test (PRBS_PASS) is available on each receive channel multifunction (MF[A−D])
terminal. To enable the report of the PRBS tests, please refer to bits 10 and 9 of MDIO register 16, 4.32768, or
5.32768. If SYNCEN is high, then PRBS_PASS latches low on the first occurrence of a bit error. SYNCEN low
releases the latch function on PRBS_PASS. MDIO comma detect settings do not affect the latching function.
3.25 MDIO Management Interface
The TLK3114SA device supports the MDIO interface as defined in clauses 22 and 45 of the IEEE 802.3ae Ethernet
specification. The MDIO allows register-based management and control of the serial links. Normal operation of the
TLK3114SA device is possible without use of this interface since all of the essential signals necessary for operations
are accessible via the device terminals. However, some additional features are accessible only through the MDIO.
The MDIO management interface consists of a bidirectional data path (MDIO) and a clock reference (MDC). The
timing required to read from the internal registers 0−31 is shown in Figure 3−19. The timing required to write to the
internal registers 0−31 is shown in Figure 3−20. The port address is defined by the external inputs PADR(0−4).
MDC
MDIO
32 “1”s
Hi-Z
0
1
1
0
A4
A0
R4
R0
0
D15 D0
Preamble
SFD
PHY Address
Data
Idle
Register Address
Read Code
Turn Around
Figure 3−19. Management Interface Read Timing
MDC
MDIO
32 “1”s
0
1
0
1
A4
A0
R4
R0
1
0
D15 D0
Preamble
SFD
Write Code
PHY Address
Data
Idle
Register Address
Turn Around
Figure 3−20. Management Interface Write Timing
The extended register address space transactions are orthogonal to register 0−31 transactions, distinguished by the
ST bytes. Extended address space registers are denoted X.Y, where X designates the device address and Y
designates the register number. The permitted device addresses are shown in Table 3−11. The DADR0 bit is defined
by an external input, while the DADR[4:1] bits are predetermined. Write transactions that address an invalid register
or device or a read-only register are ignored. Read transactions that address an invalid register return a 0. Read
transactions that address an invalid device are ignored.
Timing for an address transaction is shown in Figure 3−21. The timing required to write to the internal registers is
shown in Figure 3−22. The timing required to read from the internal registers is shown in Figure 3−23. The timing
required to read from the internal registers and then increment the active address for the next transaction is shown
in Figure 3−24.
3−20