TLK3114SA_13 Datasheet, PDF (53/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

BIT(S)
15:8
7
6:3
2
1:0
NAME
Reserved
Local fault
Reserved
TX link status
Reserved
Table 3−32. PHY XS Status 1 Register (Register 4.1)
DESCRIPTION
Read is ignored.
Logical OR of register 4.8, bits 10 and 11.
Read is ignored.
1 = Link is up
0 = Link is down
Latches low until read.
Read is ignored.
READ/WRITE
Read-only
Read-only
Read-only
Read-only
Read-only
BIT(S)
15:1
0
Table 3−33. PHY XS Speed Ability Register (Register 4.4)
NAME
DESCRIPTION
Reserved
Read returns all 0s.
10G capable
Read returns 1.
READ/WRITE
Read-only
Read-only
BIT(S)
15:6
5
4
3:1
0
Table 3−34. Devices in Package Register (Register 4.5)
NAME
DESCRIPTION
Reserved
Read is ignored.
DTE XS present
1 = Device is configured as a DTE XS.
0 = Device is configured as a PHY XS.
PHY XS present
1 = Device is configured as a PHY XS.
0 = Device is configured as a DTE XS.
Not applicable
Read returns all 0s.
Clause 22 registers present Read returns 1.
READ/WRITE
Read-only
Read-only
Read-only
Read-only
Read-only
BIT(S)
15
14
13:12
11
10
9:0
Table 3−35. 10G PHY XS Status 2 Register (Register 4.8)
NAME
DESCRIPTION
Device present
Read returns 1.
Device present
Read returns 0.
Reserved
Read is ignored.
Transmit local fault
1 = Transmit fault detected
0 = No transmit fault detected
Latches high until read.
Receive local fault
1 = Receive fault detected
0 = No receive fault detected
Latches high until read.
Reserved
Read is ignored.
READ/WRITE
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
BIT(S)
15:13
12
11:4
3
2
1
0
Table 3−36. 10G PHY XGXS Lane Status Register (Register 4.24)
NAME
DESCRIPTION
Reserved
Read is ignored.
Lane alignment
1 = PHY XGXS transmit lanes aligned
0 = PHY XGXS transmit lanes not aligned
Reserved
Read is ignored.
Lane D sync
Lane D is synchronized.
Lane C sync
Lane C is synchronized.
Lane B sync
Lane B is synchronized.
Lane A sync
Lane A is synchronized.
READ/WRITE
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
MDIO registers 4.32768−4.32781 are analogous to registers 16−29. The following table cross references the
appropriate register definition.
3−34