TLK3114SA_13 Datasheet, PDF (18/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

TERMINAL
NAME NUMBER
DADR0
U1
MDC
U2
MDIO
U3
PADR(0−4)
R1, T1,
T3, T2, R2
Table 2−5. Management Data Interface
TYPE
DESCRIPTION
LVTTL input
LVTTL input
LVTTL I/O
LVTTL input
Management MMD address. DADR0 is the externally set device address, which configures PHY
XS or DTE XS according to Table 3−11.
Management data clock. MDC is the clock reference for the transfer of management data to and
from the protocol device.
Management data I/O. MDIO is the bidirectional serial data path for the transfer of management
data to and from the protocol device.
Management PHY address. Device address PADR(0−4) is the externally set physical address
given to this device used to distinguish one device from another.
TERMINAL
NAME NUMBER
CODE
P1
TYPE
LVTTL input†
CONFIG0
CONFIG1
C2, D2
LVTTL input‡
ENABLE
LPEN(A−D)
A1
C3, D3,
P3, R3
LVTTL input†
LVTTL input‡
MF(A−D)
A16, B16,
T16, U16
LVTTL output
PRBSEN
J1
LVTTL input‡
PSYNC
C1
LVTTL input‡
RSTN
B1
LVTTL input†
SYNCEN
D1
LVTTL input†
TESTEN
P2
LVTTL input‡
† _{With an internal pullup resistor}
‡ _{With an internal pulldown resistor}
Table 2−6. Miscellaneous Terminals
DESCRIPTION
Encode enable. When CODE is high, the 8-b/10-b encoder and decoder is enabled.
Configuration terminals. These terminals put the device under one of the three operation modes:
00 = Transceiver mode
01 = Transmit-only mode
10 = Receive-only mode
11 = Repeater mode
Standby enable. When this terminal is held low, the device is in a low-power state. When high, the
device operates normally.
Internal loop enable, channels A−D. When high, the serial output for each channel is internally
looped back to its serial input.
Multifunction outputs, channels A−D. The functions of these terminals are enabled via the MDIO.
Currently defined functions are:
Terminal indicates 1 for HSTL, 0 for SSTL_2 signaling (default),
LOS (loss of signal) for each channel,
COMMA_DET (K28.5 character detected) for each channel, and
PRBS_STATUS (pseudorandom bit stream test status) for each channel.
PRBS enable. When this terminal is asserted high, the PRBS generator and comparator circuits
are inserted into the transmit and receive data paths on all channels. PRBS_PASS is indicated on
the MFx terminals once they are enabled using MDIO.
Channel synchronization enable. When PSYNC is high, all transmit data is latched on the rising
and falling edges of TCA and all receive data is valid on the rising and falling edges of RCA.
Chip reset (FIFO clear). Pulling this terminal low recenters the transmit skew buffers, receive
channel synchronization FIFOs, and resets MDIO flags.
Comma detect enable. When this terminal is high, comma detection and byte alignment for all
channels are enabled.
Test mode enable. This terminal is used for manufacturing test. This terminal must be left
unconnected or tied low.
2−5