TLK3114SA_13 Datasheet, PDF (15/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

The terminals are grouped in tables by functionality, such as clocks, serial side data, parallel data, etc. The terminal
numbers are also listed for convenient reference.
TERMINAL
NAME NUMBER
RCA
A11
RCB
F17
RCC
M17
RCD
U11
RFCP
J3
RFCN
J2
TCA
A10
TCB
F16
TCC
M16
TCD
U10
Table 2−1. Clock Terminals
XGMII
NAME
TYPE
DESCRIPTION
RX_CLK
HSTL/SSTL_2
output
Receive data clock, channel A. The data on RDA(0–9) is output on the rising and falling
edges of RCA. When PSYNC is high, RCA acts as the receive clock for all channels.
This terminal has internal series termination to provide direct connection to a 50-Ω
transmission line.
Receive data clock, channels B–D. When PSYNC is low, the data on RDx(0–9) is output
on the rising and falling edges of the receive clocks. When PSYNC is high, these terminals
N/A
HSTL/SSTL_2 _{are duplicates of RCA.}
output
These terminals have internal series termination to provide direct connection to a 50-Ω
transmission line.
N/A
PECL
compatible or
LVDS input
Differential reference input clock. This differential pair accepts LVDS- or PECL-compatible
signals. When interfacing with 3.3-V PECL, ac-coupling is required. An on-chip 100-Ω
termination resistor is placed differentially between the terminals. Internal biasing is
provided.
TX_CLK
HSTL/SSTL_2 Transmit data clock, channel A. The data on TDA(0–9) is latched on the rising and falling
input
edges of TCA. When PSYNC is high, TCA acts as the transmit clock for all channels.
N/A
HSTL/SSTL_2
input
Transmit data clock, channels B–D. When PSYNC is low, the data on TDx(0–9) is latched
on the rising and falling edges of the transmit clocks. When PSYNC is high, these terminals
are undefined.
TERMINAL
NAME
NUMBER
RXAP, RXAN
RXBP, RXBN
RXCP, RXCN
RXDP, RXDN
B5, B6
F2, G2
M2, L2
T5, T6
TXAP, TXAN
TXBP, TXBN
TXCP, TXCN
TXDP, TXDN
D5, D6
F4, G4
M4, L4
P5, P6
Table 2−2. Serial Side Data Terminals
TYPE
DESCRIPTION
PECL-compatible
input
Receive differential pairs, channels A–D. High-speed serial inputs with on-chip 100-Ω
differential termination. Each input pair is terminated differentially across an on-chip
100-Ω resistor (see Figure 4−9 and Figure 4−10). These terminals have internal biasing.
PECL-compatible
output
Transmit differential pairs, channels A–D. High-speed serial outputs.
2−2