TLK3114SA_13 Datasheet, PDF (17/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

Table 2−3. Parallel Data Terminals (Continued)
TERMINAL
NAME NUMBER
TDA[0:7]
C8, B8, A8,
E9, D9, C9,
E10, D10
TDA8
C10
TDA9
B10
TDB[0:7]
TDC[0:7]
TDD[0:7]
F13, F14,
F15, G13,
G15, G16,
H13, H15
M13, M14,
M15, L13,
L15, L16,
K13, K15
R8, T8, U8,
N9, P9, R9,
N10, P10
TDB8
H16
TDC8
K16
TDD8
R10
TDB9
J13
TDC9
J15
TDD9
T10
XGMII
NAME
TXD[0:7]
TXC0
N/A
TXD[8:15]
TXD[16:23]
TXD[24:31]
TXC1
TXC2
TXC3
N/A
TYPE
DESCRIPTION
HSTL/SSTL_2 Transmit data terminals, channel A. Parallel data on this bus is clocked on the rising
input
and falling edges of TCA.
HSTL/SSTL_2
input
Transmit data/KGEN, channel A. When CODE is low, this terminal is the ninth bit of
an 8-b/10-b encoded byte to be transmitted. When CODE is high, this terminal acts
as the K-character generator indicator. When this terminal is high, it causes the data
on TDA(0−7) to be encoded into a K-character.
HSTL/SSTL_2 Transmit data terminal, channel A. When CODE is low, this terminal is the tenth bit
input
of an 8-b/10-b encoded byte. When CODE is high, this terminal is ignored.
HSTL/SSTL_2
input
Transmit data terminals, channels B–D. When PSYNC is low, parallel data on this
bus is clocked on the rising and falling edges of the transmit channel clock (TCB,
TCC, TCD). When PSYNC is high, data on these buses is clocked on the rising and
falling edges of TCA.
HSTL/SSTL_2
input
Transmit data/KGEN, channels B–D. When PSYNC is low, data on these terminals
is clocked on the rising and falling edges of the transmit channel clock (TCB, TCC,
or TCD). When PSYNC is high, data on these terminals is clocked on the rising and
falling edges of TCA.
When CODE is low, these terminals are the ninth bit of an 8-b/10-b encoded byte
to be transmitted. When CODE is high, these terminals act as the K-character
generator indicator. When driven high, these terminals cause the data on TDx(0−7)
to be encoded into a K-character.
HSTL/SSTL_2
input
Transmit data terminal, channels B–D. When PSYNC is low, data on these terminals
is clocked on the rising and falling edges of the transmit channel clock (TCB, TCC,
TCD). When PSYNC is high, data on these terminals is clocked on the rising and
falling edges of TCA.
When CODE is low, these terminals are the tenth bit of an 8-b/10-b encoded byte.
When CODE is high, these terminals are ignored.
Table 2−4. JTAG Test Port Interface
TERMINAL
NAME NUMBER
TYPE
DESCRIPTION
TCLK
A3
LVTTL input
JTAG clock. TCLK clocks state information and test data into and out of the device during the
operation of the test port.
TDI
B3
LVTTL input†
JTAG input data. TDI serially shifts test data and test instructions into the device during the operation
of the test port.
TDO
A2
LVTTL output
TMS
B2
LVTTL input†
† _{With an internal pullup resistor}
JTAG output data. TDO serially shifts test data and test instructions out of the device during operation
of the test port. When the JTAG port is not in use, TDO is in a high-impedance state.
JTAG mode select. TMS controls the state of the internal test-port controller.
2−4