TLK3114SA_13 Datasheet, PDF (32/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

3.18 Inter-Packet Gap Management
When in the 10-Gbps ethernet XGXS operational mode, the TLK3114SA device replaces the idle codes (see
Table 3−5) during the IPG with the necessary codes to perform all channel alignment, byte alignment, and clock
tolerance compensation as defined in IEEE 802.3ae, subclause 48.2.4.2. According to clause 46, a valid packet must
begin on channel A. However, due to variable packet sizes, the IPG can begin on any channel. The TLK3114SA
device replaces idle codes latched on the same TCA (TX_CLK) clock edge as the end of packet code with /K/ codes
(as shown in Figure 3−12).
Packet
IPG
TDA[7:0] I I S D D D D ... D D D D I I I I I I
Input
TDB[7:0] I I D D D D D ... D D D T I I I I I I
TDC[7:0] I I D D D D D ... D D D I I I I I I I
TDD[7:0] I I D D D D D ... D D D I I I I I I I
TXA K R S D D D D ... D D D D A R R K K R
Output
TXB K R D D D D D ... D D D T A R R K K R
TXC K R D D D D D ... D D D K A R R K K R
TXD K R D D D D D ... D D D K A R R K K R
S = Start of Packet
D = Data
T = End of Packet
A = K28.3
K = K28.5
R = K28.0
I = Idle
Figure 3−12. Inter-Packet Gap Management
The subsequent idles in the IPG are replaced by columns of channel alignment codes (K28.3), byte alignment codes
(K28.5), or clock tolerance compensation codes (K28.0). The state machine, which governs the IPG replacement
procedure, is illustrated in Figure 3−13, with notation defined in Table 3−8. Note that any IPG management state
transitions to send data if the IPG is terminated.
The repetition of the A pattern on each serial channel allows the FIFOs to remove or add the required phase delay
to align the data from all four channels for output on a single edge of the receive clock for channel A, RCA, as shown
in Figure 3−14.
3−13