TLK3114SA_13 Datasheet, PDF (21/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

In serdes mode, the receive data bus for each channel outputs 10-bit wide 8-b/10-b encoded data on RDx[0:9]. The
8-b/10-b encoded data input to the differential high-speed serial receive terminals is deserialized with the first bit (bit
0) output on RDx0 and the last bit (bit 9) output on RDx9. Data is output relative to both the rising and falling edges
of the receive clock.
CODE
Low
High
Table 3−3. Parallel Data Modes
PARALLEL INTERFACE DATA OPERATION
Serdes mode. On-chip 8-b/10-b encoder/decoder is disabled. Data on TDx[0:9] and RDx[0:9] is treated as 8-b/10-b encoded
data.
Transceiver mode. Enables 8-b/10-b encode/decode for each channel. Data TDx[0:7] and RDx[0:7] are treated as uncoded
data. TDx8 is used as the K-character generator control. RDx8 is the K-character indicator to the host device. Data on TDx9 is
ignored. RDx9 goes high on either a disparity or code error.
In transceiver mode, the transmit data bus for each channel accepts 8-bit wide parallel data at the TDx[0:7] terminals.
Data is sampled on the rising and falling edges of the transmit clock as shown in Figure 3−1. The data is first aligned
to the reference clock (RFCP/RFCN), then 8-b/10-b encoded and passed to the serializer. The generation of
K-characters on each channel is controlled by TDx8 (KGEN). When KGEN is asserted along with the 8 bits of data
TDx[0:7], the appropriate 8-b/10-b K-character is transmitted.
In transceiver mode, the receive data bus for each channel outputs an 8-bit wide parallel data on RDx[0:7]. Reception
of K-characters is reported on RDx8 (KFLAG). When KFLAG is asserted, the 8 bits of data on RDx[0:7] must be
interpreted as a K-character. If an error is uncovered in decoding the data, KFLAG and RDx9 (RX_ER) are asserted
and 0xFE is placed on the receive data bus for that channel.
3.5 Transmit Data Bus Timing
For each channel, the transmitter portion of the TLK3114SA device latches the data on transmit data bus TDx[0:9]
on both the rising and falling edges of the transmit data clock, as shown in Figure 3−1. Depending on the state of the
PSYNC terminal, the transmit data clock is either TCA (channel sync mode) or the individual transmit channel clocks,
TCA−TCD (independent channel mode). When in the channel sync mode, signals on TCB, TCC, and TCD are
ignored.
TCA, TCB,
TCC, TCD
TDx[9:0]
th
tsu
Data
tsu
th
Data
Figure 3−1. Transmit Interface Timing
3.6 Transmission Latency
For each channel, the data transmission latency of the TLK3114SA device is defined as the delay from the rising or
falling edge of the selected transmit clock when valid data is on the transmit data terminals to the serial transmission
of bit 0, as shown in Figure 3−2. The minimum latency (T_LATENCY) is 71 bit times; the maximum is 120 bit times. There
are approximately 20 bit times required for the 8-b/10-b encoder.
3−2