TLK3114SA_13 Datasheet, PDF (22/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

TXxP
TXxN
TDx[7:0]
td(T_Latency)
Byte to be Transmitted
10-Bit Code Transmitted
TCx
Figure 3−2. Transmitter Latency
3.7 Channel Clock to Serial Transmit Clock Synchronization
The TLK3114SA device requires an external differential reference clock, RFCP/N, for the on-chip phase-locked loop
(PLL) and the clock/data recovery loop. To compensate for arbitrary clock phase tolerance differences between the
reference clock and the data aligned to the transmit clock, a small FIFO in the parallel transmit data path on each
channel is employed. This FIFO has a depth of four bytes.
The reference clock and the transmit data clock(s) are assumed to be from a common source and only phase
misaligned due to different path delays as shown in Figure 3−3 and Figure 3−4. The reference clock is multiplied in
frequency 10x to produce the internal serialization clock. The internal serialization clock is used to clock out the serial
transmit data.
Protocol Device
Channel
Logic
Channel A
TCA
TX
FIFO
TLK3114SA
Data A
Serdes
Core
Channel
Logic
Channel B
TX
FIFO
Data B
Serdes
Core
Channel
Logic
Channel C
TX
FIFO
Data C
Serdes
Core
Channel
Logic
Channel D
TX
FIFO
Data D
Serdes
Core
RFCP/RFCN
Xtal OSC
Figure 3−3. Transmit and Reference Clock Relationship (Channel Sync Mode)
3−3