TLK3114SA_13 Datasheet, PDF (29/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

Protocol Device
Channel
Logic
Channel
Logic
Channel
Logic
Channel
Logic
Channel A
RCA
Channel B
Channel C
Channel D
TLK3114SA
RX
FIFO
Data A
RX
FIFO
RCLKA
Data B
RCLKB
RX
FIFO
Data C
RCLKC
RX
FIFO
Data D
RCLKD
Serdes
Core
Serdes
Core
Serdes
Core
Serdes
Core
RFCP/RFCN
Xtal OSC
Figure 3−9. Receive and Reference Clock Relationship (Synchronized Channel Modes)
The de-skew of the four channels into a single column of data is accomplished by alignment of the receive FIFOs
on each channel to a K28.3 K-character sent during the inter-packet gap (IPG) between data packets or during initial
link synchronization. The K28.3 code (referred to as the A or alignment code) is transmitted on the first column
following the end of the data packet as shown in Figure 3−12.
The column deskew state machine is provided in Figure 3−10. The status of column alignment can be monitored by
reading bit 12 of MDIO registers 4.24 or 5.24 for global alignment, or bits 3:0 of MDIO registers 4.24 or 5.24 for
particular channels. Bit 4 of MDIO registers 23, 4.32775, and 5.32775 indicates when a realignment has occurred.
3−10