TLK3114SA_13 Datasheet, PDF (44/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

BIT(S)
15
14
13
12
11
10:9
8
7
6
5
4
3
2
1
0
Table 3−18. Global Configuration Register Bit Definitions (Register 16)
NAME
DESCRIPTION
Reserved
Read returns 0, writes are ignored.
De-skew state machine
1 = Enable deskew state machine described in Figure 3−10.
0 = Disable deskew state machine (default).
Channel synchronization
state machine
1 = Enable channel synchronization state machine described in Figure 3−7.
0 = Disable channel synchronization state machine (default).
IPG management state
machine
1 = Enable IPG management state machine described in Figure 3−13.
0 = Disable IPG management state machine (default).
Clock tolerance
compensation
1 = Enable clock tolerance compensation.
0 = Disable clock tolerance compensation (default).
Multifunction pin output
Multifunction (MF[A−D]) terminal configuration.
Bit 10
0
0
1
1
Bit 9
0
1
0
1
Output
HSTL = 1, SSTL_2 = 0 (default)
1 = Comma detected, 0 = data
Register 22, bits 3−0 (LOS)
Register 22, bits 7−4 (PRBS pass)
Loss of signal detection
1 = Enable LOS condition described in Table 3−6 for all channels (default).
0 = Disable this function.
Configuration: Config1
Configuration bits (see Table 3−10), default value = 0.
When CONFIG1 = low, this bit can be set to 1.
When CONFIG1 = high, this bit is read-only.
Logically ORed with external input CONFIG1.
Configuration: Config0
Configuration bits (see Table 3−10), default value = 0
When CONFIG0 = low, this bit can be set to 1.
When CONFIG0 = high, this bit is read-only.
Logically ORed with external input CONFIG0.
Preemphasis: Pre2
Programmable preemphasis control (see Table 3−9), default value = 0.
Preemphasis: Pre1
Programmable preemphasis control (see Table 3−9), default value = 0.
Reserved
Read returns a 0, writes are ignored.
PRBS enable
1 = Enable PRBS internal generation and verification on all channels
0 = Normal operation (default).
When PRBSEN = low, this bit can be set to 1.
When PRBSEN = high, this bit is read-only.
Logically ORed with PRBSEN.
Comma detect enable
1 = Enable K28.5 code detection and bit alignment on all channels (default).
0 = Disable K28.5 code detection on all channels.
Logically AND’ed with SYNCEN.
Reserved
Read returns a 0, writes are ignored.
READ/WRITE
Read-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read/Write
Read/Write
Read/Write
3−25