TLK3114SA_13 Datasheet, PDF (50/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

BIT(S)
15:5
4
3
2
1
0
Table 3−24. Channel Synchronization Status Register (Register 23)
NAME
DESCRIPTION
Reserved
Read returns all 0s.
Channel allign flag
1 = Channel deskew circuit has realigned to a K28.3 /A/ code word on all
channels.
0 = No /A/ has been detected.
After being read, this bit is reset to 0.
Channel D receive FIFO
collision error
1 = Collision error is detected to cause the receive FIFO self reset.
0 = No error.
After being read, this bit is reset to 0.
Channel C receive FIFO
collision error
1 = Collision error is detected to cause the receive FIFO self reset.
0 = No error.
After being read, this bit is reset to 0.
Channel B receive FIFO
collision error
1 = Collision error is detected to cause the receive FIFO self reset.
0 = No error.
After being read, this bit is reset to 0.
Channel A receive FIFO
collision error
1 = Collision error is detected to cause the receive FIFO self reset.
0 = No error.
After being read, this bit is reset to 0.
READ/WRITE
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
3−31