TLK3114SA_13 Datasheet, PDF (4/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

List of Illustrations
Figure
Title
Page
1−1 System Block Diagram (Chip-to-Chip Implementation) . . . . . . . . . . . . . . . 1−1
1−2 System Block Diagram (PCS Implementation) . . . . . . . . . . . . . . . . . . . . . . 1−2
1−3 System Block Diagram (Backplane Interconnect Implementation) . . . . . 1−2
1−4 TLK3114SA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4
1−5 Block Diagram of Individual Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
2−1 TLK3114SA GNT/GPV-Package Terminal Diagram . . . . . . . . . . . . . . . . . . 2−1
3−1 Transmit Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3−2 Transmitter Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3
3−3 Transmit and Reference Clock Relationship (Channel Sync Mode) . . . . 3−3
3−4 Transmit and Reference Clock Relationship
(Independent Channel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
3−5 Receive Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4
3−6 Receiver Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
3−7 Channel Synchronization State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3−8 End-of-Packet Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3−9 Receive and Reference Clock Relationship
(Synchronized Channel Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10
3−10 Column De-Skew State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
3−11 Receive and Reference Clock Relationship
(Independent Channel Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−12
3−12 Inter-Packet Gap Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−14
3−13 IPG Management State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−14
3−14 Channel Synchronization Using Alignment Code . . . . . . . . . . . . . . . . . . . . 3−15
3−15 Clock Tolerance Compensation: Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−16
3−16 Clock Tolerance Compensation: Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−17
3−17 Output Differential Voltage Under Preemphasis . . . . . . . . . . . . . . . . . . . . . 3−18
3−18 Repeater-Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−19
3−19 Management Interface Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−20
3−20 Management Interface Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−20
3−21 Management Interface Extended Space Address Timing . . . . . . . . . . . . . 3−21
3−22 Management Interface Extended Space Write Timing . . . . . . . . . . . . . . . 3−21
3−23 Management Interface Extended Space Read Timing . . . . . . . . . . . . . . . 3−21
3−24 Management Interface Extended Space Read and Increment Timing . . 3−21
4−1 Differential and Common-Mode Output Voltage Definitions . . . . . . . . . . . 4−4
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