TLK3114SA_13 Datasheet, PDF (23/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

Protocol Device
Channel
Logic
Channel
Logic
Channel
Logic
Channel
Logic
Channel A
TCA
Channel B
TCB
Channel C
TCC
Channel D
TCD
TX
FIFO
TLK3114SA
Data A
TX
FIFO
Data B
TX
FIFO
Data C
TX
FIFO
Data D
Serdes
Core
Serdes
Core
Serdes
Core
Serdes
Core
RFCP/RFCN
Xtal OSC
Figure 3−4. Transmit and Reference Clock Relationship (Independent Channel Mode)
3.8 Receive Data Bus Timing
For each channel, the receiver portion of the TLK3114SA device outputs the recovered deserialized data on the
receive data bus TDx[0:9] on both the rising and falling edges of the receive data clock, as shown in Figure 3−5.
Depending on the state of PSYNC terminal the receive data clock is either RCA (channel sync mode) or the individual
receive channel clocks, RCA−RCD (independent channel mode). Terminals RCB, RCC, and RCD are also strobed
to match RCA in channel sync mode.
RCA, RCB,
RCC, RCD
th
tsu
tsu
th
RDx[9:0]
Data
Data
Figure 3−5. Receive Interface Timing
3.9 Data Reception Latency
For each channel, the serial-to-parallel data latency is the time from when the first bit arrives at the receiver input until
it is output in the aligned parallel word with RDx0 received as first bit, as shown in Figure 3−6. The minimum latency
(R_LATENCY) is 84 bit times; the maximum is 225 bit times. The 8-b/10-b encoder, channel de-skew, and CTC all
contribute to the maximum latency.
3−4