TLK3114SA_13 Datasheet, PDF (27/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

3.13.1 Channel State Descriptions
UNSYNC—This is the initial state for each channel upon device power up or reset. If a LOS condition is detected,
the channel state is set to UNSYNC. In this state, the TLK3114SA device has the comma detect circuit active and
makes code word alignment adjustments based on the position of a comma in the incoming data stream. While in
this state, the TLK3114SA device sets the lane sync bit to 0 for the particular channel in MDIO registers 4.24 and 5.24,
bits 3:0, indicating the lane is not synchronized. The channel state transitions to the ACQ1 state upon the detection
of a comma.
NOTE: When the lane sync bit equals 0, it causes a local fault to be output on the receive data bus.
ACQ1—During this state the comma detect circuit is active but code word realignment is disabled. The TLK3114SA
device remains in this state until either a comma is detected in the same code word alignment position as found in
state UNSYNC or a decode error is encountered. While in this state, the lane sync bit for the particular channel
remains deasserted indicating the lane is not synchronized. A decode or running disparity error returns the channel
state to UNSYNC. A detected comma causes the channel state to transition to ACQ2.
NOTE: When the lane sync bit equals 0, it causes a local fault to be output on the receive data bus.
ACQ2—During this state, the comma detect circuit is active but code word realignment is disabled. The TLK3114SA
device remains in this state until either a comma is detected in the same code word alignment position as found in
state UNSYNC or a decode error is encountered. While in this state, the lane sync bit for the particular channel
remains deasserted indicating the lane is not synchronized. A decode or running disparity error returns the channel
state to UNSYNC. A detected comma causes the channel state to transition to ACQ3.
NOTE: When the lane sync bit equals 0, it causes a local fault to be output on the receive data bus.
ACQ3—During this state, the comma detect circuit is active but code word realignment is disabled. The TLK3114SA
device remains in this state until either a comma is detected or a decode error encountered. While in this state, the
lane sync bit for the particular channel remains deasserted indicating the lane is not synchronized. A decode or
running disparity error returns the channel state to UNSYNC. A detected comma causes the channel state to
transition to SYNC.
NOTE: When the lane sync bit equals 0, it causes a local fault to be output on the receive data bus.
SYNC—This is the normal state for receiving data. When in this state, the TLK3114SA device sets the lane sync bit
to 1 for the particular channel in MDIO registers 4.24 and 5.24, bits 3:0, indicating the lane has been synchronized.
During this state the comma detect circuit is active but code word realignment is disabled. A decode or running
disparity error causes the channel state to transition to MISS1.
MISS1—When entering this state an internal error counter is cleared. If the next three consecutive codes are decoded
without error, the channel state reverts back to SYNC. If a decode or running disparity error is detected, the channel
state transitions to MISS2.
MISS2—When entering this state an internal error counter is cleared. If the next three consecutive codes are decoded
without error, the channel state reverts back to MISS1. If a decode or running disparity error is detected, the channel
state transitions to MISS3.
MISS3—When entering this state an internal error counter is cleared. If the next three consecutive codes are decoded
without error, the channel state reverts back to MISS1. If a decode or running disparity error is detected, the channel
state transitions to UNSYNC.
3.14 End-of-Packet Error Detection
Because of their unique data patterns, /A/ (K28.3), /K/ (K28.5), and /T/ (K29.7) catch running disparity errors that may
have propagated undetected from previous codes in a packet. Running disparity errors detected by these control
codes at the end of the packets cause the previous data codes to be reported as errors (0xFE) to allow the protocol
device to reject the packet (see Figure 3−8).
3−8