TLK3114SA_13 Datasheet, PDF (36/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

Packet
IPG
RXA K R S D D D D ... D D D D A R R K S D
Input
RXB K R D D D D D ... D D D T A R R K D D
RXC K R D D D D D ... D D D K A R R K D D
RXD K R D D D D D ... D D D K A R R K D D
Dropped Column
RDA[7:0] I I S D D D D ... D D D D I I I S D D
Output
RDB[7:0] I I D D D D D ... D D D T I I I D D D
RDC[7:0] I I D D D D D ... D D D I I I I D D D
RDD[7:0] I I D D D D D ... D D D I I I I D D D
S = Start of Packet
D = Data
T = End of Packet
A = K28.3
K = K28.5
R = K28.0
I = Idle
Figure 3−16. Clock Tolerance Compensation: Drop
The /R/ code is disparity neutral, allowing its removal or insertion without affecting the current running disparity of each
channel’s serial stream.
The clock tolerance compensation circuit also converts XAUI A, K, and R characters to XGMII idles, as illustrated in
Figure 3−16.
3.20 Parallel-to-Serial Shift Register
The parallel-to-serial shift register on each channel takes in 10-bit wide data from either the 8-b/10-b encoders, if
enabled, or directly from the transmit data bus and converts it to a serial stream. The shift register is clocked by the
internally generated bit clock, which is 10 times the reference clock (RFCP/RFCN) frequency. The least significant
bit (LSB) for each channel is transmitted first.
3.21 Serial-to-Parallel Shift Register
For each channel, serial data is received on the RXxP/RXxN terminals. The interpolator and clock recovery circuit
locks to the data stream if the clock to be recovered is within ±100 PPM of the internally generated bit rate clock. The
recovered clock retimes the input data stream. The serial data is then clocked into the serial-to-parallel shift registers.
If enabled, the 10-bit wide parallel data is then fed into 8-b/10-b decoders. If the TLK3114SA device is configured in
one of the synchronized channel modes, the parallel data for each channel is fed into a FIFO buffer where the output
is synchronized to RCA. If the TLK3114SA device is configured in one of the independent channel modes, the parallel
data for each channel is output synchronized to each channel’s recovered clock.
Transmitting data across PCB or cables attenuates the high frequency content of the signal. This reduces the timing
margin for the receiver and clock recovery circuits. The TLK3114SA device applies a filter at the receiver to invert
the effects of the interconnect, or equalize and recover some of the lost margin. This maximizes the receiver’s ability
to recover transmitted data.
3−17