TLK3114SA_13 Datasheet, PDF (52/66 Pages) Texas Instruments – 10-Gbps XAUI Transceiver

BIT(S)
15:4
3
2
1
0
NAME
Reserved
Channel D counter
select
Channel C counter
select
Channel B counter
select
Channel A counter
select
Table 3−26. Error Counter Control Register (Register 25)
DESCRIPTION
Read returns all 0s.
0 = Running disparity error counter (default).
1 = Decode error counter
0 = Running disparity error counter (default).
1 = Decode error counter
0 = Running disparity error counter (default).
1 = Decode error counter
0 = Running disparity error counter (default).
1 = Decode error counter
READ/WRITE
Read-only
Read/Write
Read/Write
Read/Write
Read/Write
BIT(S)
NAME
15:0 Error count
Table 3−27. Channel A Error Count (Register 26)
DESCRIPTION
READ/WRITE
Channel A running disparity or decode error count value selected by register 25, bit 0.
After being read, this counter is reset to 0.
Read-only
BIT(S)
NAME
15:0 Error count
Table 3−28. Channel B Error Count (Register 27)
DESCRIPTION
Channel B running disparity or decode error count value selected by register 25, bit 1.
After being read, this counter is reset to 0.
READ/WRITE
Read-only
BIT(S)
NAME
15:0 Error count
Table 3−29. Channel C Error Count (Register 28)
DESCRIPTION
READ/WRITE
Channel C running disparity or decode error count value selected by register 25, bit 2.
After being read, this counter is reset to 0.
Read-only
BIT(S)
NAME
15:0 Error count
Table 3−30. Channel D Error Count (Register 29)
DESCRIPTION
READ/WRITE
Channel D running disparity or decode error count value selected by register 25, bit 3.
After being read, this counter is reset to 0.
Read-only
Table 3−31. PHY XS Control 1 Register (Register 4.0)
BIT(S)
NAME
DESCRIPTION
15 Reset
Logically ORed with the inverse of RSTN terminal.
1 = Global resets including FIFO clear.
0 = Normal operation (default)
14 Loopback
1 = Enable loopback mode on all channels.
0 = Disable loopback mode on all channels (default).
13 Speed selection (LSB) Not applicable. Read returns 1.
12:7 Reserved
Not applicable. Read returns all 0s.
6 Speed selection (MSB) Not applicable. Read returns 1.
5:2 Speed selection
Not applicable. Read returns all 0s.
1:0 Reserved
Not applicable. Read returns all 0s.
† _{After reset, this bit is set to 1; it automatically sets itself back to 0 on the next MDC clock cycle.}
READ/WRITE
Read/Write
Self Clearing†
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
3−33