TLK3118 Datasheet, PDF (9/57 Pages) Texas Instruments – Redundant XAUI Transceiver

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TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
Table 2. Valid XGMII Channel Encodings (continued)
Data Bus (TXD[x: x-7] or TXC(3:0) or RXC(3:0)
RXD[x: x-7])
FB
1
FC
1
FD
1
FE
1
FF
1
Description
Start (only valid in Channel A)
Reserved
Terminate
Transmit error propagation
Reserved
Comma Detect and 8B/10B Decoding
When parallel data is clocked into a parallel to serial converter, the byte boundary that was associated with the
parallel data is lost in the serialization of the data. When the serial data is received and converted to parallel
format again, a method is needed to be able to recognize the byte boundary again. Generally this is
accomplished through the use of a synchronization pattern. This is a unique a pattern of 1’s and 0’s that either
cannot occur as part of valid data or is a pattern that repeats at defined intervals. 8B/10B encoding contains a
character called the comma (b’0011111’ or b’1100000’) which is used by the comma detect circuit to align the
received serial data back to its original byte boundary. The decoder detects the K28.5 comma, generating a
synchronization signal aligning the data to their 10-bit boundaries for decoding. It then converts the data back
into 8-bit data. It is important to note that the comma can be either a (b’0011111’) or the inverse (b’1100000’)
depending on the running disparity. The TLK3118 decoder will detect both patterns.
The reception of K-characters is reported by the assertion of receive control pin, RXC (3:0) for the corresponding
byte on the XGMII receive bus. When a code word error or running disparity error is detected in the decoded
data received on a serial link, the receive control pin is asserted and a 0xFE is placed on the receive data bus for
that channel, as shown in Table 3.
Event
Normal Data
Normal K-character
Code word error or running disparity error
Table 3. Receive Data Controls
Receive Data Bus RXD[x: 7-x]
XX
Valid K-code
FE
RXC(3:0)
0
1
1
Channel Initialization and Synchronization
The TLK3118 has a synchronization state machine which is responsible for handling link initialization and
synchronization for each channel. The initialization and synchronization state diagram is provided in Figure 10.
The status of any channel can be monitored by reading MDIO register 4:5.24.3:0.
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