TLK3118 Datasheet, PDF (6/57 Pages) Texas Instruments – Redundant XAUI Transceiver

TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
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Detailed Description (continued)
A completely active secondary XAUI channel will allow transition from primary to secondary channels within a
few XGMII clock cycles. During the transition from primary to secondary XAUI channels, the data on each byte of
the XGMII bus will be 0xFE (code violation), which is the ERROR indication, or local fault indication (based on
provisioned register value).
Also, when the primary input IDLE = HIGH, the secondary transmit XAUI channel transmits legal A/K/R
characters instead of the 8B/10B encoded packet stream. When IDLE = LOW, the transmit packet stream is
bridged to both sets of XAUI output channels.
Re-Timer Operation (RETIM = HIGH)
When RETIM is asserted high, the TLK3118 will operate as a full duplex XAUI re-timer. All the functions of
transceiver operations are performed with the exception input from the XGMII. The recovered data on each XAUI
channel is de-serialized, de-skewed, aligned to the reference clock, and re-serialized. In the re-timer mode inputs
from the TXD (31:0) are ignored.
Note that when RETIM is high, the XAUI A receive data is eventually routed out to the XAUI B transmit serial
lines. Similarly, the XAUI B receive data is eventually routed out to the XAUI A transmit serial lines.
The TLK3118 re-timer mode default condition will be to enable the XGMII receive output bus, RXD (31:0).
However, a software setting is available to put the RXD bus into a high-impedance state desired for power
savings. The TLK3118 can be configured, via MDIO or pin, to monitor the recovered data on either XAUI
channel. If the re-timer monitoring mode is enabled, the state of the A/B pin will determine which XAUI channel
recovered data is output on the XGMII receive output bus. If A/B is toggled when in re-timer monitor mode, the
data on each byte of the XGMII receive output bus will be 0xFE (code violation) for several XGMII clock cycles,
or local fault (based on the provisioned register value).
Parallel Interface Clocking
The TLK3118 supports source centered timing on the XGMII transmit input bus. The timing supported is the
timing defined in P802.3ae Clause 46 with the TCLK centered within the transmit data bit timing, as shown in
Figure 6.
TCLK
TXD[31:0]
TXC(3:0)
t_h
t_su
Data
t_su
t_h
Data
Figure 6. Transmit Interface Timing – Source Centered
On the receive data path, the data is synchronized and output referenced to RCLK, with the RCLK placed in the
center of the data window, as shown in Figure 7. RCLK is derived from the transmit reference clock. A FIFO,
placed on the output of the serial to parallel conversion logic for each serial link, compensates for channel skew,
clock phase and frequency tolerance differences between the recovered clocks for each serial links and the
receive output clock, RCLK. This FIFO has a total depth of nine ten bit entries, giving 40 bit time deskew
(channel-to-channel skew) alignment capability. See Table 94 and Table 95 for more details on XGMII timing.
RCLK
RXD[31:0]
RXC(3:0)
t_h
t_su
Data
t_su
t_h
Data
Figure 7. Receive Interface Timing
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