TLK3118 Datasheet, PDF (40/57 Pages) Texas Instruments – Redundant XAUI Transceiver

TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
www.ti.com
Table 76. VTP_MACRO_CONTROL
Bit(s)
4/5.32920.15
4/5.32920.14
4/5.32920.13
4/5.32920.12
4/5.32920.11
4/5.32920.10
4/5.32920.9
4/5.32920.8
4/5.32920.7
4/5.32920.6
4/5.32920.5
Address:0x8098
Default:0xBB20
Name
Description
VTP 1 EN
1 = Enable VTP1 macro (Default)
0 = Disable VTP1 macro
Set 0 for Power down or feed through modes
VTP 1 CLK
1 = Enable CLK to change VTP1 macro settings
0 = Disable CLK (Default)
VTP 1 CLRZ
1 = Initializes VTP1 macro (Default)
Enable should be high to reset bits
VTP 1 LOCK
When set to 1 locks VTP1 bits in their current state. LOCK must be low
when setting the VTP1 bits
VTP 2 EN
1 = Enable VTP2 macro (Default)
0 = Disable VTP2 macro
Set 0 for Power down or feed through modes
VTP 2 CLK
1 = Enable CLK to change VTP2 macro settings
0 = Disable CLK (Default)
VTP 2 CLRZ
1 = Initializes VTP2 macro (Default)
Enable should be high to reset bits
VTP 2 LOCK
When set to 1 locks VTP2 bits in their current state. LOCK must be low
when setting the VTP2 bits
RESERVED
Termination Enable
Active LOW termination enable. When 0 enables the termination resistance
on the HSTL input.
Driver Enable
1 = Switching on the HSTL outputs (32 data, 4 control and clock) on the
XGMII side is enabled
0 = Switching on the HSTL outputs (32 data, 4 control and clock) on the
XGMII side is disabled
Access
RW
Bit(s)
4/5.32921.15
4/5.32921.14
4/5.32921.13
4/5.32921.12
4/5.32921.11
4/5.32921.10
4/5.32921.9
4/5.32921.8
4/5.32921.7
4/5.32921.6
N1IN
N2IN
N3IN
N4IN
N5IN
P1IN
P2IN
P3IN
P4IN
P5IN
Table 77. VTP1_BIT_CONTROL
Address:0x8099
Name
Description
N1 signal to be loaded when VTP1 EN = 0
N2 signal to be loaded when VTP1 EN = 0
N3 signal to be loaded when VTP1 EN = 0
N4 signal to be loaded when VTP1 EN = 0
N5 signal to be loaded when VTP1 EN = 0
P1 signal to be loaded when VTP1 EN = 0
P2 signal to be loaded when VTP1 EN = 0
P3 signal to be loaded when VTP1 EN = 0
P4 signal to be loaded when VTP1 EN = 0
P5 signal to be loaded when VTP1 EN = 0
Default:0xA0C0
Access
RW
To configure the drive strength values for VTP macros manually, perform the following steps (also see Figure 24)
:
1. Disable switching activity on the HSTL outputs by setting VTP_MACRO_CONTROL[5] = LOW.
2. Unlock the macros by writing 0xAA00 to VTP_MACRO_CONTROL register.
3. Enable both macros by writing 0xEE00 followed by 0xAA00 to VTP_MACRO_CONTROL register (this will
toggle the CLK for both macros).
4. Clear the macros by writing 0xCC00 followed by 0xAA00 to VTP_MACRO_CONTROL register (this will
toggle the CLRZ for both macros).
5. Write the desired pull-down and pull-up strength values to the VTP1_BIT_CONTROL and
VTP2_BIT_CONTROL registers for macro 1 and 2 respectively.
6. Write 0xEE00 followed by 0xAA00.
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