TLK3118 Datasheet, PDF (45/57 Pages) Texas Instruments – Redundant XAUI Transceiver

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TERMINAL
NAME
NO.
TDI
W19
TDO
V19
TMS
U19
TCK
Y20
TRST_N
U20
TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
Table 82. JTAG Test Port Interface
TYPE DESCRIPTION
LVCMOS
2.5V Input
(Internal
Pullup)
LVCMOS
2.5V Output
LVCMOS
2.5V Input
(Internal
Pullup)
LVCMOS
2.5V Input
LVCMOS
2.5V Input
(Internal
Pullup)
JTAG Input Data TDI is used to serially shift test data and test instructions into the device
during the operation of the test port.
JTAG Output Data TDO is used to serially shift test data and test instructions out of the
device during operation of the test port. When the JTAG port is not in use, TDO is in a high
impedance state.
JTAG Mode Select TMS is used to control the state of the internal test-port controller.
JTAG Clock TCK is used to clock state information and test data into and out of the device
during the operation of the test port.
JTAG Test Reset– TRST_N is used to reset the JTAG logic into system operational mode.
TERMINAL
NAME
NO.
MDIO
U2
MDC
T2
DVAD(4:0)
T1, T3, U1
V1, W1
Table 83. Management Data Interface
TYPE DESCRIPTION
LVCMOS
2.5V I/O
LVCMOS
2.5V Input
LVCMOS
2.5V Input
Management Data I/O MDIO is the bi-directional serial data path for the transfer of
management data to and from the protocol device.
Management Data Clock MDC is the clock reference for the transfer of management data
to and from the protocol device.
Management PHY Address Device Address: DVAD (4:1) is the externally set physical
address given to this device used to distinguish one device from another. DVAD (0) is
actually used to determine whether the device responds as a DTE (=1) or PHY (=0) XGXS
device (4.xxx or 5.xxx on register accesses). These are typically pulled up or pulled down in
the system application.
TERMINAL
NAME
NO.
A_B
D7
RETIM
N1
IDLE
N19
RSTN
D9
Table 84. Miscellaneous Pins
TYPE DESCRIPTION
LVCMOS
2.5V Input
LVCMOS
2.5V Input
LVCMOS
2.5V Input
LVCMOS
2.5V Input
XAUI Lane Select In Retime mode, A/B selects which data is reflected on the XGMII
outputs. In Redundant Transceiver Modes, A/B selects whether XAUI A or XAUI B data is
reflected on the XGMII output interface, if so enabled.
A_B = 1 -> A Side Selected
A_B = 0 -> B Side Selected
Re-Timer Mode Enable When RETIM is high, serial inputs from XAUI Channels A RX are
synchronized and output on XAUI Channels B TX, and vice-versa.
IDLE When RETIME is low, and IDLE is high, IDLE codes (Valid AKR Sequences) will be
sent out to the non selected serial interface instead of bridged XGMII transmit traffic packet
data. When RETIME is low, and IDLE is low, both XAUI A and XAUI B transmit data will
reflect the actual XGMII TX packet data. When RETIME is high, this pin should be
considered a don’t care input.
Chip Reset When asserted low, this signal reinitializes the entire device. Must be asserted
for at least 10 uS after device power up.
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