TLK3118 Datasheet, PDF (31/57 Pages) Texas Instruments – Redundant XAUI Transceiver

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TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
Table 39. RX_LANE_ALIGN_STATUS
Address:0x8015
Default:0x0000
Bit(s)
Name
Description
4/5.32789.15: Align state
12
Current lane alignment FSM state
4/5.32789.0 Lane Alignment FIFO
collision
Collision status for lane alignment FIFO. When high, indicates that there is
collision error in lane alignment FIFO.
Access
RO
RO/LH
Table 40. RX_CHANNEL_SYNC_STATUS
Bit(s)
4/5.32790.11
Address:0x8016
Default:0x0000
Name
Description
Channel Synchronization
status for all lanes
1 = Channel synchronization is achieved in all lanes
0 = Channel synchronization is lost in one or more lanes
Access
RO/LL
Table 41. BIT_ORDER
Bit(s)
4/5.32791. 3
4/5.32791. 2
4/5.32791. 1
4/5.32791. 0
Address:0x8017
Default:0x0005
Name
Description
XGMII RX bit order
When high, reverses the order of bits in the parallel data sent from XAUI RX
A and B for each lane.
XAUI RX bit order
When high, reverses the order of bits in the parallel data received from
SERDES macros for XAUI RX A and B for each lane.
XGMII TX bit order
When high, reverses the order of bits in the parallel data received from the
XGMII interface each lane.
XAUI TX bit order
When high, reverses the order of bits in the parallel data sent to the
SERDES TX macro for each lane.
Access
RW
Table 42. LOOPBACK_CONTROL
Bit(s)
4/5.32792. 1
4/5.32792. 0
Address:0x8018
Default:0x0000
Name
Description
XAUI side loopback
When high, loops back 32 bit data and 4 control bits from the RX path to the
TX path. (4/5.0.14 should be 0 else no effect)
XGMII side loopback
When 1, loops back 40 bit data from TX path to the RX path (4/5.0.14 should
be 0 else no effect)
Access
RW
Table 43. TX_BYPASS_CONTROL
Bit(s)
4/5.32793.15
4/5.32793.11
4/5.32793.7
4/5.32793.6
4/5.32793.5
4/5.32793.4
Address:0x8019
Default:0x0000
Name
Description
TX IPG management bypass When high, disables IPG management (replacing Idle XGMII characters with
/A/K/R/Q/ code-words) in transmit side.
TX CTC Bypass
When high, disables clock tolerance compensation in transmit side
Lane 3 8B10B encoder by- When high, disables 8B10B encoding on the corresponding lane
pass
Lane 2 8B10B encoder by-
pass
Lane 1 8B10B encoder by-
pass
Lane 0 8B10B encoder by-
pass
Access
RW
31