TLK3118 Datasheet, PDF (44/57 Pages) Texas Instruments – Redundant XAUI Transceiver

TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
www.ti.com
Table 80. Serial Side Data Pins
TERMINAL
NAME
NO.
TDP30/TDN30
TDP20/TDN20
TDP10/TDN10
TDP00/TDN00
W7,Y7 U8,V8
W9,Y9
U10,V10
TDP31/TDN31
TDP21/TDN21
TDP11/TDN11
TDP01/TDN01
W15,Y15
U16,V16
W17,Y17
U18,V18
RDP30/RDN30
RDP20/RDN20
RDP10/RDN10
RDP00/RDN00
U6,V6 W5,Y5
U4,V4 W3,Y3
RDP31/RDN31
RDP21/RDN21
RDP11/RDN11
RDP01/RDN01
U14,V14
W13,Y13
U12,V12
W11,Y11
TYPE
CML Output
CML Output
CML Input
CML Input
DESCRIPTION
Transmit Differential Pairs, XAUI Lane A High-speed serial outputs. Minimum bit time
320 ps.
Transmit Differential Pairs, XAUI Lane B High speed serial outputs. Minimum bit time
320 ps.
Receive Differential Pairs, XAUI Lane A High-speed serial inputs with on-chip 100-Ω
differential termination. Each input pair is terminated differentially across an on chip 100-Ω
resistor. Minimum bit time 320 ps.
Receive Differential Pairs, XAUI Lane B High speed serial inputs with on-chip 100-Ω
differential termination. Each input pair is terminated differentially across an on chip 100-Ω
resistor. Minimum bit time 320 ps.
TERMINAL
NAME
NO.
TXD(31:0)
B9, A8, C8,
B8, C7, C6,
D5, C4, B7
A7, B6, A6
G3, H4, H3
B5, B4, B3
B2, G1, G2
H1, H2, J2
J1, K1, L1
L4, L2, M2
M3, M4
TXC(3:0)
C9, D3 C2,
K4
RXD(31:0)
C11, D11
D17, D13
D12, C12
B12, C17
C14, C13
B13, B17
D19, D18
E19, C19
H18, C18
B19, F18
F20, G19
G20, H19
K17, H20
K16, J20
L17, K19
K20, L20
RXC(3:0)
B11, C15
J17, K18
XGMII
NAME
TXD[31:0]
TXC0
RXD(31:0)
RXC(3:0)
Table 81. Parallel Data Pins
TYPE
DESCRIPTION
HSTL/ Input
Transmit Data Pins Parallel data on this bus is clocked on the rising and falling
edge of TCLK.
HSTL/ Input
Transmit Data Control XGMII Control inputs. This bus is clocked on both edges
of TCLK.
Receive Data Pins Parallel data on this bus is valid on the rising and falling
HSTL/ Output edge of RCLK. These pins have internal series termination to provide direct
connection to a 50-Ω transmission line.
Receive Data Control XGMII Control Outputs. This data is valid on both the
HSTL/ Output rising and falling edge of RCLK. These pins have internal series termination to
provide direct connection to a 50-Ω transmission line.
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