TLK3118 Datasheet, PDF (11/57 Pages) Texas Instruments – Redundant XAUI Transceiver

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TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
NOTE:
The Lane Sync bit = '0' will cause a local fault to be output on the receive data bus.
ACQ2
During this state, the comma detect circuit is active but code word re-alignment is disabled. The TLK3118 will
remain in this state until either a comma is detected in the same code word alignment position as found in state
UNSYNC or a decode error is encountered. While in this state, the Lane Sync bit for the particular channel will
remain de-asserted indicating the lane is not synchronized. A decode or running disparity error will return the
channel state to UNSYNC. A detected comma will cause the channel state to transition to ACQ3.
ACQ3
During this state the comma detect circuit is active but code word re-alignment is disabled. The TLK3118 will
remain in this state until either a comma is detected or a decode error encountered. . While in this state, the
Lane Sync bit for the particular channel will remain de-asserted indicating the lane is not synchronized.7 A
decode or running disparity error will return the channel state to UNSYNC. A detected comma will cause the
channel state to transition to SYNC.
SYNC
This is the normal state for receiving data. When in this state, the TLK3118 will set the Lane Sync bit to '1' for the
particular channel in the MDIO register bits 4:5.24.3:0 indicating the lane has been synchronized. During this
state the comma detect circuit is active but code word re-alignment is disabled. A decode or running disparity
error will cause the channel state to transition to MISS1.
MISS1
When entering this state an internal error counter is cleared. If the next four consecutive codes are decoded
without error, the channel state reverts back to SYNC. If a decode or running disparity error is detected, the
channel state will transition to MISS2.
MISS2
When entering this state an internal error counter is cleared. If the next four consecutive codes are decoded
without error, the channel state reverts back to MISS1. If a decode or running disparity error is detected, the
channel state will transition to MISS3.
MISS3
When entering this state an internal error counter is cleared. If the next four consecutive codes are decoded
without error, the channel state reverts back to MISS1. If a decode or running disparity error is detected, the
channel state will transition to UNSYNC.
End-of-Packet Error Detection
Because of their unique data patterns, /A/ (K28.3), /K/ (K28.5), and /T/ (K29.7) will catch running disparity errors
that may have propagated undetected from previous codes in a packet. Running disparity errors detected by
these control codes at the end of packets will cause the previous data codes to be reported as errors (0xFE) to
allow the protocol device to reject the packet (see Figure 11).
11