TLK3118 Datasheet, PDF (19/57 Pages) Texas Instruments – Redundant XAUI Transceiver

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TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
Parallel to Serial
The parallel-to-serial shift register on each channel takes in data and converts it to a serial stream. The shift
register is clocked by the internally generated bit clock, which is 10 times the reference clock
(REFCLKP/REFCLKN) frequency. The least significant bit (LSB) for each channel is transmitted first.
Serial to Parallel
For each channel, serial data is received on the RDPx/RDNx pins. The interpolator and clock recovery circuit will
lock to the data stream if the clock to be recovered is within ±200 PPM of the internally generated bit rate clock.
The recovered clock is used to retime the input data stream. The serial data is then clocked into the
serial-to-parallel shift registers. If enabled, the 10-bit wide parallel data is then fed into 8b/10b decoders.
High-Speed CML Output
The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up
resistors requires no external components. The line can be directly coupled or AC coupled. Under many
circumstances, AC coupling is desirable.
TDP
50 Ω
RDP
Transmission Line
V_DDT
50 Ω 3 kΩ
+
_
50 Ω 9 kΩ
TDN
Transmitter
50 Ω
Transmission Line
Media
RDN
GND
Receiver
Figure 18. Example High Speed I/O AC Coupled Mode
Standard Current Mode Logic (CML) drivers usually require external components. The disadvantage of the
external edge control is a limited edge rate due to package and line parasitic. The CML driver on TLK3118 has
on-chip 50-Ω termination resistors terminated to VDDT therefore provides optimum performance for increased
speed requirements. The transmitter output driver is highly configurable allowing, output amplitude and
pre-emphasis to be turned to a channel's individual requirements. An internal voltage reference derived from
VDDT is also available to provide the target for output amplitude control loop. This reference is enabled by
holding register bit 4/5.32900.6 low and will result in a nominal output amplitude of ~1010mV differential pk-pk for
100% swing. Register bit 4/5.32900.5 is used to switch between AC and DC coupled at the receiver. When AC
couple is selected, the receiver input is internally biased to 2×VDDT/3 which is the optimum voltage for input
sensitivity. As the input and output references are derived from VDDT, the tolerance of this supply will dominate
the accuracy of the internal reference. Applications requiring higher tolerance output amplitude are advised to
provide a high accuracy external reference.
When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal is
attenuated due to the skin effect of the media. This causes a “smearing” of the data eye when viewed on an
oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In order to
provide equalization for the high frequency loss, 2-tap finite impulse response (FIR) transmit pre-emphasis is
implemented. In a 1-tap FIR pre-emphasis, differential swing is increased or “pre-emphasized” for the bit
immediately following a transition and subsequently reduced or “de-emphasized” for run lengths greater than
one, as shown in Figure 19. This provides additional high frequency energy to compensate for PCB or cable
loss.
19