TLK3118 Datasheet, PDF (37/57 Pages) Texas Instruments – Redundant XAUI Transceiver

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TLK3118
Redundant XAUI Transceiver
SLLS628A – DECEMBER 2004 – REVISED APRIL 2005
Table 63. SERDES_PLL_CONTROL
Bit(s)
4/5.32903.15
Address:0x8087
Name
PLL Enable
1 = Enabled
0 = Disabled
Description
Default:0x8000
Access
RW
Table 64. SERDES_SYNC_STATUS
Address:0x8088
Default:0x0000
Bit(s)
Name
Description
4/5.32904.15: Sync
8
Synchronous detect. When high, indicates a comma character has been
detected for lanes 7~0 (Feature not supported. Bits made available for future
use)
4/5.32904.7:0 Loss of link
Loss of link. When high, indicates that link at the receiver 7~0 lanes is lost
(Feature not supported. Bits made available for future use)
Access
RO
Table 65. SERDES_TESTFAIL_CONTROL
Bit(s)
4/5.32905.15
Address:0x8089
Default:0x8000
Name
Description
Test fail select
Test fail select controls. According to these selection bits, following Test fail
signals will be given out as testfail_mux_out to the Output Pins
0 = TX TESTFAIL selected
1 = RX TESTFAIL selected
Table 66. SERDES_TEST_CONFIG⁽¹⁾
Address:0x808A
Default:0x0000
Bit(s)
Name
Description
4/5.32906.15: TESTCFG[15:14]
14
Reserved
4/5.32906.13: EQTESTMD
12
TESTCFG[13:12]
00 – Equalizer test mode disabled (Default)
01 – 16 Parametric devices observable
10 – 17 Parametric devises are observable
11 – High impedance mode
4/5.32906.11 PADLPBACK TESTCFG[11] 0 – Pad loop back disabled (Default)
1 – Pad loop back enabled
TESTCFG[10] should be enabled else no effect
4/5.32906.10 LOOPBACK TESTCFG[10] 0 – Loop back disabled (Default)
1 – Loop back enabled ( For Internal Test Pattern Verification)
4/5.32906.9 BSIN
Enable boundary scan inputs. This bit has no affect on transmit SERDES
macro.
4/5.32906.8 BSOUT
Enable boundary scan outputs. This bit has no affect on receive SERDES
macro.
4/5.32906.7:4 AFR TESTCFG[7:4]
Asynchronous frequency ramp mode.
Refer Table 67: Asynchronous frequency ramp mode (Default 4’b0000)
4/5.32906.3 TESTCLK TESTCFG[3]
0 – PLL bypass disabled (Default)
1 – PLL bypass enabled
4/5.32906.2:0 TESTPATT TESTCFG[2:0]
000 – Test pattern gen/verification disabled (Default)
001 – Clock pattern gen/verification enabled
010 – 2⁷ - 1 PRBS gen/verification enabled
011 – 2²³â€“ 1 PRBS gen/verification enabled
100 – Low frequency clock pattern
101 – Reserved
110 – Reserved
111 – Reserved
(1) These control bits are only for vendor testing only. Customer should leave them at their default values
Access
RW
Access
RW
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